rheaswitch.h

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 380 行 · 第 1/2 页

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :rheaswitch.h
//
//   Date of Module Modification:1/2/04
//   Date of Generation :1/2/04
//
//
//========================================================================

#ifndef _RHSW_ARM__H
#define _RHSW_ARM__H

#include "result.h"
#include "test.h"
#include "mapping.h"
#include "global_types.h"
#include "testaccess.h"
#include "error.h"

// Entry linked to a constant value
#define MPU_nDSP 1

#define IS_A_MPU_PERIPHERAL       1
#define IS_NOT_A_MPU_PERIPHERAL   0

#define IS_A_DSP_PERIPHERAL       1
#define IS_NOT_A_DSP_PERIPHERAL   0


#ifdef DOLO_DC
//BEGIN INC GENERATION
//--------------------------------------
// part merged from omap1510 project
#define  MPU_RHEASWITCH_UART1  (MPU_RHEASWITCH_BASE_ADD + 0x00)
#define  MPU_RHEASWITCH_UART2  (MPU_RHEASWITCH_BASE_ADD + 0x40) // offset address=1 (32 bits aligned)
#define  MPU_RHEASWITCH_UART3  (MPU_RHEASWITCH_BASE_ADD + 0x80) // offset address=2 (32 bits aligned)

#define  RHSW_ARM_CNF  ALIGNOrNotOn32Bits_from8bits(0x00)
#define  RHSW_ARM_STA  ALIGNOrNotOn32Bits_from8bits(0x01)


#define RHSW_ARM_CNF_UART1_REG  *(REGISTER_UWORD8*)  (MPU_RHEASWITCH_UART1+RHSW_ARM_CNF)
#define RHSW_ARM_STA_UART1_REG  *(REGISTER_UWORD8*)  (MPU_RHEASWITCH_UART1+RHSW_ARM_STA)
#define RHSW_ARM_CNF_UART2_REG  *(REGISTER_UWORD8*)  (MPU_RHEASWITCH_UART2+RHSW_ARM_CNF)
#define RHSW_ARM_STA_UART2_REG  *(REGISTER_UWORD8*)  (MPU_RHEASWITCH_UART2+RHSW_ARM_STA)
#define RHSW_ARM_CNF_UART3_REG  *(REGISTER_UWORD8*)  (MPU_RHEASWITCH_UART3+RHSW_ARM_CNF)
#define RHSW_ARM_STA_UART3_REG  *(REGISTER_UWORD8*)  (MPU_RHEASWITCH_UART3+RHSW_ARM_STA)
// end merge

#endif


//Register Offset
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_OFFSET                                                                  0x000
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_OFFSET                                                                  0x004
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_OFFSET                                                                  0x040
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_OFFSET                                                                  0x044
#define            RHSW_ARM_RHSW_ARM_CNF_TPU_OFFSET                                                                    0x080
#define            RHSW_ARM_RHSW_ARM_STA_TPU_OFFSET                                                                    0x084
#define            RHSW_ARM_RHSW_ARM_CNF_TSP_OFFSET                                                                    0x0C0
#define            RHSW_ARM_RHSW_ARM_STA_TSP_OFFSET                                                                    0x0C4
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_OFFSET                                                                   0x100
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_OFFSET                                                                   0x104
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_OFFSET                                                                 0x140
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_OFFSET                                                                 0x144
#define            RHSW_ARM_RHSW_ARM_CNF_USIM_OFFSET                                                                   0x180
#define            RHSW_ARM_RHSW_ARM_STA_USIM_OFFSET                                                                   0x184




//RHSW_ARM_RHSW_ARM_CNF_MCSI1
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1                                                                         REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_MCSI1_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_DSP_PERIPH_LOCK_POS                                                       1
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_DSP_PERIPH_LOCK_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_DSP_PERIPH_LOCK_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_ARM_PERIPH_LOCK_POS                                                       0
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_ARM_PERIPH_LOCK_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_ARM_PERIPH_LOCK_RES_VAL                                                   0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_MCSI1
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1                                                                         REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_MCSI1_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_BOTH_LCK_ERR_POS                                                     3
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_BOTH_LCK_ERR_NUMB                                                    1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_BOTH_LCK_ERR_RES_VAL                                                 0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_ITPEND_ERR_POS                                                       2
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_ITPEND_ERR_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_ITPEND_ERR_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_DMAREQ_ERR_POS                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_DMAREQ_ERR_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_DMAREQ_ERR_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_ERR_NIRQ_POS                                                         0
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_ERR_NIRQ_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_RHSW_ERR_NIRQ_RES_VAL                                                     0x1
//R/W


//RHSW_ARM_RHSW_ARM_CNF_MCSI2
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2                                                                         REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_MCSI2_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_DSP_PERIPH_LOCK_POS                                                       1
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_DSP_PERIPH_LOCK_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_DSP_PERIPH_LOCK_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_ARM_PERIPH_LOCK_POS                                                       0
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_ARM_PERIPH_LOCK_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_ARM_PERIPH_LOCK_RES_VAL                                                   0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_MCSI2
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2                                                                         REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_MCSI2_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_BOTH_LCK_ERR_POS                                                     3
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_BOTH_LCK_ERR_NUMB                                                    1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_BOTH_LCK_ERR_RES_VAL                                                 0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_ITPEND_ERR_POS                                                       2
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_ITPEND_ERR_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_ITPEND_ERR_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_DMAREQ_ERR_POS                                                       1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_DMAREQ_ERR_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_DMAREQ_ERR_RES_VAL                                                   0x0
//R

#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_ERR_NIRQ_POS                                                         0
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_ERR_NIRQ_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_RHSW_ERR_NIRQ_RES_VAL                                                     0x1
//R/W


//RHSW_ARM_RHSW_ARM_CNF_TPU
//-------------------
#define            RHSW_ARM_RHSW_ARM_CNF_TPU                                                                           REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_CNF_TPU_OFFSET)


#define            RHSW_ARM_RHSW_ARM_CNF_TPU_DSP_PERIPH_LOCK_POS                                                         1
#define            RHSW_ARM_RHSW_ARM_CNF_TPU_DSP_PERIPH_LOCK_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_CNF_TPU_DSP_PERIPH_LOCK_RES_VAL                                                     0x0
//R

#define            RHSW_ARM_RHSW_ARM_CNF_TPU_ARM_PERIPH_LOCK_POS                                                         0
#define            RHSW_ARM_RHSW_ARM_CNF_TPU_ARM_PERIPH_LOCK_NUMB                                                        1
#define            RHSW_ARM_RHSW_ARM_CNF_TPU_ARM_PERIPH_LOCK_RES_VAL                                                     0x1
//R/W


//RHSW_ARM_RHSW_ARM_STA_TPU
//-------------------
#define            RHSW_ARM_RHSW_ARM_STA_TPU                                                                           REG16(MPU_RHEASWITCH_BASE_ADD+RHSW_ARM_RHSW_ARM_STA_TPU_OFFSET)


#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_BOTH_LCK_ERR_POS                                                       3
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_BOTH_LCK_ERR_NUMB                                                      1
#define            RHSW_ARM_RHSW_ARM_STA_TPU_RHSW_BOTH_LCK_ERR_RES_VAL                                                   0x0
//R