watchdog32khz.h
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//R/W
#define WATCHDOG32KHZ_WCLR_32_PRE_POS 5
#define WATCHDOG32KHZ_WCLR_32_PRE_NUMB 1
#define WATCHDOG32KHZ_WCLR_32_PRE_RES_VAL 0x1
//R/W
#define WATCHDOG32KHZ_WCLR_32_PTV_POS 2
#define WATCHDOG32KHZ_WCLR_32_PTV_NUMB 3
#define WATCHDOG32KHZ_WCLR_32_PTV_RES_VAL 0x0
//R/W
//R/W
//WATCHDOG32KHZ_WCRR
//-------------------
#define WATCHDOG32KHZ_WCRR_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WCRR_OFFSET*coeff16_arm+0)
#define WATCHDOG32KHZ_WCRR_16_0_TIME_COUNTER_POS 0
#define WATCHDOG32KHZ_WCRR_16_0_TIME_COUNTER_NUMB 32
#define WATCHDOG32KHZ_WCRR_16_0_TIME_COUNTER_RES_VAL 0x000FFFFF
//R/W
#define WATCHDOG32KHZ_WCRR_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WCRR_OFFSET*coeff16_arm+2)
#define WATCHDOG32KHZ_WCRR_16_2_TIME_COUNTER_POS 0
#define WATCHDOG32KHZ_WCRR_16_2_TIME_COUNTER_NUMB 32
#define WATCHDOG32KHZ_WCRR_16_2_TIME_COUNTER_RES_VAL 0x000FFFFF
//R/W
#define WATCHDOG32KHZ_WCRR_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WCRR_OFFSET*coeff32_arm)
#define WATCHDOG32KHZ_WCRR_32_TIME_COUNTER_POS 0
#define WATCHDOG32KHZ_WCRR_32_TIME_COUNTER_NUMB 32
#define WATCHDOG32KHZ_WCRR_32_TIME_COUNTER_RES_VAL 0x000FFFFF
//R/W
//WATCHDOG32KHZ_WLDR
//-------------------
#define WATCHDOG32KHZ_WLDR_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WLDR_OFFSET*coeff16_arm+0)
#define WATCHDOG32KHZ_WLDR_16_0_TIME_LOAD_POS 0
#define WATCHDOG32KHZ_WLDR_16_0_TIME_LOAD_NUMB 32
#define WATCHDOG32KHZ_WLDR_16_0_TIME_LOAD_RES_VAL 0xFFF00000
//R/W
#define WATCHDOG32KHZ_WLDR_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WLDR_OFFSET*coeff16_arm+2)
#define WATCHDOG32KHZ_WLDR_16_2_TIME_LOAD_POS 0
#define WATCHDOG32KHZ_WLDR_16_2_TIME_LOAD_NUMB 32
#define WATCHDOG32KHZ_WLDR_16_2_TIME_LOAD_RES_VAL 0xFFF00000
//R/W
#define WATCHDOG32KHZ_WLDR_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WLDR_OFFSET*coeff32_arm)
#define WATCHDOG32KHZ_WLDR_32_TIME_LOAD_POS 0
#define WATCHDOG32KHZ_WLDR_32_TIME_LOAD_NUMB 32
#define WATCHDOG32KHZ_WLDR_32_TIME_LOAD_RES_VAL 0xFFF00000
//R/W
//WATCHDOG32KHZ_WTGR
//-------------------
#define WATCHDOG32KHZ_WTGR_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WTGR_OFFSET*coeff16_arm+0)
#define WATCHDOG32KHZ_WTGR_16_0_TTGR_VALUE_POS 0
#define WATCHDOG32KHZ_WTGR_16_0_TTGR_VALUE_NUMB 32
#define WATCHDOG32KHZ_WTGR_16_0_TTGR_VALUE_RES_VAL 0x00000000
//R/W
#define WATCHDOG32KHZ_WTGR_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WTGR_OFFSET*coeff16_arm+2)
#define WATCHDOG32KHZ_WTGR_16_2_TTGR_VALUE_POS 0
#define WATCHDOG32KHZ_WTGR_16_2_TTGR_VALUE_NUMB 32
#define WATCHDOG32KHZ_WTGR_16_2_TTGR_VALUE_RES_VAL 0x00000000
//R/W
#define WATCHDOG32KHZ_WTGR_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WTGR_OFFSET*coeff32_arm)
#define WATCHDOG32KHZ_WTGR_32_TTGR_VALUE_POS 0
#define WATCHDOG32KHZ_WTGR_32_TTGR_VALUE_NUMB 32
#define WATCHDOG32KHZ_WTGR_32_TTGR_VALUE_RES_VAL 0x00000000
//R/W
//WATCHDOG32KHZ_WWPS
//-------------------
#define WATCHDOG32KHZ_WWPS_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WWPS_OFFSET*coeff16_arm+0)
//R
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WSPR_POS 4
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WSPR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WSPR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WTGR_POS 3
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WTGR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WTGR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WLDR_POS 2
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WLDR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WLDR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WCRR_POS 1
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WCRR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WCRR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WCLR_POS 0
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WCLR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_0_W_PEND_WCLR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WWPS_OFFSET*coeff16_arm+2)
//R
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WSPR_POS 4
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WSPR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WSPR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WTGR_POS 3
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WTGR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WTGR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WLDR_POS 2
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WLDR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WLDR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WCRR_POS 1
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WCRR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WCRR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WCLR_POS 0
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WCLR_NUMB 1
#define WATCHDOG32KHZ_WWPS_16_2_W_PEND_WCLR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WWPS_OFFSET*coeff32_arm)
//R
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WSPR_POS 4
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WSPR_NUMB 1
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WSPR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WTGR_POS 3
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WTGR_NUMB 1
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WTGR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WLDR_POS 2
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WLDR_NUMB 1
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WLDR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WCRR_POS 1
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WCRR_NUMB 1
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WCRR_RES_VAL 0x0
//R
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WCLR_POS 0
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WCLR_NUMB 1
#define WATCHDOG32KHZ_WWPS_32_W_PEND_WCLR_RES_VAL 0x0
//R
//WATCHDOG32KHZ_WSPR
//-------------------
#define WATCHDOG32KHZ_WSPR_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WSPR_OFFSET*coeff16_arm+0)
#define WATCHDOG32KHZ_WSPR_16_0_WSPR_VALUE_POS 0
#define WATCHDOG32KHZ_WSPR_16_0_WSPR_VALUE_NUMB 32
#define WATCHDOG32KHZ_WSPR_16_0_WSPR_VALUE_RES_VAL 0x00000000
//R/W
#define WATCHDOG32KHZ_WSPR_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WSPR_OFFSET*coeff16_arm+2)
#define WATCHDOG32KHZ_WSPR_16_2_WSPR_VALUE_POS 0
#define WATCHDOG32KHZ_WSPR_16_2_WSPR_VALUE_NUMB 32
#define WATCHDOG32KHZ_WSPR_16_2_WSPR_VALUE_RES_VAL 0x00000000
//R/W
#define WATCHDOG32KHZ_WSPR_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WSPR_OFFSET*coeff32_arm)
#define WATCHDOG32KHZ_WSPR_32_WSPR_VALUE_POS 0
#define WATCHDOG32KHZ_WSPR_32_WSPR_VALUE_NUMB 32
#define WATCHDOG32KHZ_WSPR_32_WSPR_VALUE_RES_VAL 0x00000000
//R/W
#endif
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