watchdog32khz.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :watchdog32khz.h
//
// Date of Module Modification:5/21/02
// Date of Generation :5/21/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _WATCHDOG32KHZ__H
#define _WATCHDOG32KHZ__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define coeff8_arm 1
#define coeff16_arm 1
#define coeff32_arm 1
//-------------------
#define WATCHDOG32KHZ_WIDR_OFFSET 0x00
#define WATCHDOG32KHZ_WD_SYSCONFIG_OFFSET 0x10
#define WATCHDOG32KHZ_WD_SYSSTATUS_OFFSET 0x14
#define WATCHDOG32KHZ_WCLR_OFFSET 0x24
#define WATCHDOG32KHZ_WCRR_OFFSET 0x28
#define WATCHDOG32KHZ_WLDR_OFFSET 0x2C
#define WATCHDOG32KHZ_WTGR_OFFSET 0x30
#define WATCHDOG32KHZ_WWPS_OFFSET 0x34
#define WATCHDOG32KHZ_WSPR_OFFSET 0x48
//WATCHDOG32KHZ_WIDR
//-------------------
#define WATCHDOG32KHZ_WIDR_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WIDR_OFFSET*coeff16_arm+0)
//R
#define WATCHDOG32KHZ_WIDR_16_0_WD_REV_POS 0
#define WATCHDOG32KHZ_WIDR_16_0_WD_REV_NUMB 8
#define WATCHDOG32KHZ_WIDR_16_0_WD_REV_RES_VAL 0x10
//R
#define WATCHDOG32KHZ_WIDR_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WIDR_OFFSET*coeff16_arm+2)
//R
#define WATCHDOG32KHZ_WIDR_16_2_WD_REV_POS 0
#define WATCHDOG32KHZ_WIDR_16_2_WD_REV_NUMB 8
#define WATCHDOG32KHZ_WIDR_16_2_WD_REV_RES_VAL 0x10
//R
#define WATCHDOG32KHZ_WIDR_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WIDR_OFFSET*coeff32_arm)
//R
#define WATCHDOG32KHZ_WIDR_32_WD_REV_POS 0
#define WATCHDOG32KHZ_WIDR_32_WD_REV_NUMB 8
#define WATCHDOG32KHZ_WIDR_32_WD_REV_RES_VAL 0x10
//R
//WATCHDOG32KHZ_WD_SYSCONFIG
//-------------------
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WD_SYSCONFIG_OFFSET*coeff16_arm+0)
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_EMUFREE_POS 5
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_EMUFREE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_EMUFREE_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_SOFTRESET_POS 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_SOFTRESET_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_SOFTRESET_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_AUTOIDLE_POS 0
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_AUTOIDLE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_0_AUTOIDLE_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WD_SYSCONFIG_OFFSET*coeff16_arm+2)
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_EMUFREE_POS 5
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_EMUFREE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_EMUFREE_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_SOFTRESET_POS 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_SOFTRESET_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_SOFTRESET_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_AUTOIDLE_POS 0
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_AUTOIDLE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_16_2_AUTOIDLE_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WD_SYSCONFIG_OFFSET*coeff32_arm)
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_EMUFREE_POS 5
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_EMUFREE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_EMUFREE_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_SOFTRESET_POS 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_SOFTRESET_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_SOFTRESET_RES_VAL 0x0
//R/W
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_AUTOIDLE_POS 0
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_AUTOIDLE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSCONFIG_32_AUTOIDLE_RES_VAL 0x0
//R/W
//WATCHDOG32KHZ_WD_SYSSTATUS
//-------------------
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WD_SYSSTATUS_OFFSET*coeff16_arm+0)
//R
//R
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_0_RESETDONE_POS 0
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_0_RESETDONE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_0_RESETDONE_RES_VAL 0x1
//R
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WD_SYSSTATUS_OFFSET*coeff16_arm+2)
//R
//R
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_2_RESETDONE_POS 0
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_2_RESETDONE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSSTATUS_16_2_RESETDONE_RES_VAL 0x1
//R
#define WATCHDOG32KHZ_WD_SYSSTATUS_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WD_SYSSTATUS_OFFSET*coeff32_arm)
//R
//R
#define WATCHDOG32KHZ_WD_SYSSTATUS_32_RESETDONE_POS 0
#define WATCHDOG32KHZ_WD_SYSSTATUS_32_RESETDONE_NUMB 1
#define WATCHDOG32KHZ_WD_SYSSTATUS_32_RESETDONE_RES_VAL 0x1
//R
//WATCHDOG32KHZ_WCLR
//-------------------
#define WATCHDOG32KHZ_WCLR_16_0 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WCLR_OFFSET*coeff16_arm+0)
//R/W
#define WATCHDOG32KHZ_WCLR_16_0_PRE_POS 5
#define WATCHDOG32KHZ_WCLR_16_0_PRE_NUMB 1
#define WATCHDOG32KHZ_WCLR_16_0_PRE_RES_VAL 0x1
//R/W
#define WATCHDOG32KHZ_WCLR_16_0_PTV_POS 2
#define WATCHDOG32KHZ_WCLR_16_0_PTV_NUMB 3
#define WATCHDOG32KHZ_WCLR_16_0_PTV_RES_VAL 0x0
//R/W
//R/W
#define WATCHDOG32KHZ_WCLR_16_2 REG16(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WCLR_OFFSET*coeff16_arm+2)
//R/W
#define WATCHDOG32KHZ_WCLR_16_2_PRE_POS 5
#define WATCHDOG32KHZ_WCLR_16_2_PRE_NUMB 1
#define WATCHDOG32KHZ_WCLR_16_2_PRE_RES_VAL 0x1
//R/W
#define WATCHDOG32KHZ_WCLR_16_2_PTV_POS 2
#define WATCHDOG32KHZ_WCLR_16_2_PTV_NUMB 3
#define WATCHDOG32KHZ_WCLR_16_2_PTV_RES_VAL 0x0
//R/W
//R/W
#define WATCHDOG32KHZ_WCLR_32 REG32(WATCHDOG32KHZ_BASE_ADDR_ARM+WATCHDOG32KHZ_WCLR_OFFSET*coeff32_arm)
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