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📄 omap_32_lcdc.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :omap_32_lcdc.h
//
//   Date of Module Modification:4/26/02
//   Date of Generation :5/2/02
//
//
//========================================================================
#include "omap_32_mapping.h"
#ifndef _LCDC__H
#define _LCDC__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            LCDC_LCD_CTRL_REG_OFFSET                                                                            0x00
#define            LCDC_LCD_TIMING_0_OFFSET                                                                            0x04
#define            LCDC_LCD_TIMING_1_OFFSET                                                                            0x08
#define            LCDC_LCD_TIMING_2_OFFSET                                                                            0x0C
#define            LCDC_LCD_STATUS_OFFSET                                                                              0x10
#define            LCDC_LCD_SUB_PANEL_OFFSET                                                                           0x14
#define            LCDC_LINE_INTERRUPT_REGISTER_OFFSET                                                                 0x18
#define            LCDC_DISPLAY_STATUS_REGISTER_OFFSET                                                                 0x1C




//LCDC_LCD_CTRL_REG
//-------------------
#define            LCDC_LCD_CTRL_REG                                                                                   REG32(LCDC_BASE_ADDR_ARM+LCDC_LCD_CTRL_REG_OFFSET)


//R/W

#define            LCDC_LCD_CTRL_REG_STN_565_POS                                                                         24
#define            LCDC_LCD_CTRL_REG_STN_565_NUMB                                                                        1
#define            LCDC_LCD_CTRL_REG_STN_565_RES_VAL                                                                     0x0
//R/W

#define            LCDC_LCD_CTRL_REG_TFT_MAP_POS                                                                         23
#define            LCDC_LCD_CTRL_REG_TFT_MAP_NUMB                                                                        1
#define            LCDC_LCD_CTRL_REG_TFT_MAP_RES_VAL                                                                     0x0
//R/W

#define            LCDC_LCD_CTRL_REG_NM_POS                                                                              22
#define            LCDC_LCD_CTRL_REG_NM_NUMB                                                                             1
#define            LCDC_LCD_CTRL_REG_NM_RES_VAL                                                                          0x0
//R/W

#define            LCDC_LCD_CTRL_REG_PLM_POS                                                                             20
#define            LCDC_LCD_CTRL_REG_PLM_NUMB                                                                            2
#define            LCDC_LCD_CTRL_REG_PLM_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_CTRL_REG_FDD_POS                                                                             12
#define            LCDC_LCD_CTRL_REG_FDD_NUMB                                                                            8
#define            LCDC_LCD_CTRL_REG_FDD_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_CTRL_REG_PXL_GATED_POS                                                                       11
#define            LCDC_LCD_CTRL_REG_PXL_GATED_NUMB                                                                      1
#define            LCDC_LCD_CTRL_REG_PXL_GATED_RES_VAL                                                                   0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LINE_INT_CLR_SEL_POS                                                                10
#define            LCDC_LCD_CTRL_REG_LINE_INT_CLR_SEL_NUMB                                                               1
#define            LCDC_LCD_CTRL_REG_LINE_INT_CLR_SEL_RES_VAL                                                            0x0
//R/W

#define            LCDC_LCD_CTRL_REG_M8B_POS                                                                             9
#define            LCDC_LCD_CTRL_REG_M8B_NUMB                                                                            1
#define            LCDC_LCD_CTRL_REG_M8B_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LCDBE_POS                                                                           8
#define            LCDC_LCD_CTRL_REG_LCDBE_NUMB                                                                          1
#define            LCDC_LCD_CTRL_REG_LCDBE_RES_VAL                                                                       0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LCD_TFT_POS                                                                         7
#define            LCDC_LCD_CTRL_REG_LCD_TFT_NUMB                                                                        1
#define            LCDC_LCD_CTRL_REG_LCD_TFT_RES_VAL                                                                     0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LINE_INT_MASK_POS                                                                   6
#define            LCDC_LCD_CTRL_REG_LINE_INT_MASK_NUMB                                                                  1
#define            LCDC_LCD_CTRL_REG_LINE_INT_MASK_RES_VAL                                                               0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LINE_INT_NIRQ_MASK_POS                                                              5
#define            LCDC_LCD_CTRL_REG_LINE_INT_NIRQ_MASK_NUMB                                                             1
#define            LCDC_LCD_CTRL_REG_LINE_INT_NIRQ_MASK_RES_VAL                                                          0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LOADMASK_POS                                                                        4
#define            LCDC_LCD_CTRL_REG_LOADMASK_NUMB                                                                       1
#define            LCDC_LCD_CTRL_REG_LOADMASK_RES_VAL                                                                    0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LCDDONEMASK_POS                                                                     3
#define            LCDC_LCD_CTRL_REG_LCDDONEMASK_NUMB                                                                    1
#define            LCDC_LCD_CTRL_REG_LCDDONEMASK_RES_VAL                                                                 0x0
//R/W

#define            LCDC_LCD_CTRL_REG_VSYNC_MASK_POS                                                                      2
#define            LCDC_LCD_CTRL_REG_VSYNC_MASK_NUMB                                                                     1
#define            LCDC_LCD_CTRL_REG_VSYNC_MASK_RES_VAL                                                                  0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LCDBW_POS                                                                           1
#define            LCDC_LCD_CTRL_REG_LCDBW_NUMB                                                                          1
#define            LCDC_LCD_CTRL_REG_LCDBW_RES_VAL                                                                       0x0
//R/W

#define            LCDC_LCD_CTRL_REG_LCD_ENABLE_POS                                                                      0
#define            LCDC_LCD_CTRL_REG_LCD_ENABLE_NUMB                                                                     1
#define            LCDC_LCD_CTRL_REG_LCD_ENABLE_RES_VAL                                                                  0x0
//R/W


//LCDC_LCD_TIMING_0
//-------------------
#define            LCDC_LCD_TIMING_0                                                                                   REG32(LCDC_BASE_ADDR_ARM+LCDC_LCD_TIMING_0_OFFSET)


#define            LCDC_LCD_TIMING_0_HBP_POS                                                                             24
#define            LCDC_LCD_TIMING_0_HBP_NUMB                                                                            8
#define            LCDC_LCD_TIMING_0_HBP_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_TIMING_0_HFP_POS                                                                             16
#define            LCDC_LCD_TIMING_0_HFP_NUMB                                                                            8
#define            LCDC_LCD_TIMING_0_HFP_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_TIMING_0_HSW_POS                                                                             10
#define            LCDC_LCD_TIMING_0_HSW_NUMB                                                                            6
#define            LCDC_LCD_TIMING_0_HSW_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_TIMING_0_PPL_POS                                                                             0
#define            LCDC_LCD_TIMING_0_PPL_NUMB                                                                            10
#define            LCDC_LCD_TIMING_0_PPL_RES_VAL                                                                         0x0
//R/W


//LCDC_LCD_TIMING_1
//-------------------
#define            LCDC_LCD_TIMING_1                                                                                   REG32(LCDC_BASE_ADDR_ARM+LCDC_LCD_TIMING_1_OFFSET)


#define            LCDC_LCD_TIMING_1_VBP_POS                                                                             24
#define            LCDC_LCD_TIMING_1_VBP_NUMB                                                                            8
#define            LCDC_LCD_TIMING_1_VBP_RES_VAL                                                                         0x0
//R/W

#define            LCDC_LCD_TIMING_1_VFP_POS                                                                             16

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