📄 omap_32_testblock.h
字号:
#define TESTBLOCK_EMIFF_PSA_LSB_EMIFF_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_EMIFF_PSA_HSB
//-------------------
#define TESTBLOCK_EMIFF_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_EMIFF_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_EMIFF_PSA_HSB_EMIFF_HSB_POS 0
#define TESTBLOCK_EMIFF_PSA_HSB_EMIFF_HSB_NUMB 20
#define TESTBLOCK_EMIFF_PSA_HSB_EMIFF_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_PUBRHEA_PSA_LSB
//-------------------
#define TESTBLOCK_PUBRHEA_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_PUBRHEA_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_PUBRHEA_PSA_LSB_PUBRHEA_LSB_POS 0
#define TESTBLOCK_PUBRHEA_PSA_LSB_PUBRHEA_LSB_NUMB 20
#define TESTBLOCK_PUBRHEA_PSA_LSB_PUBRHEA_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_PUBRHEA_PSA_HSB
//-------------------
#define TESTBLOCK_PUBRHEA_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_PUBRHEA_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_PUBRHEA_PSA_HSB_PUBRHEA_HSB_POS 0
#define TESTBLOCK_PUBRHEA_PSA_HSB_PUBRHEA_HSB_NUMB 20
#define TESTBLOCK_PUBRHEA_PSA_HSB_PUBRHEA_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_PRIVRHEA_PSA_LSB
//-------------------
#define TESTBLOCK_PRIVRHEA_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_PRIVRHEA_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_PRIVRHEA_PSA_LSB_PRIVRHEA_LSB_POS 0
#define TESTBLOCK_PRIVRHEA_PSA_LSB_PRIVRHEA_LSB_NUMB 20
#define TESTBLOCK_PRIVRHEA_PSA_LSB_PRIVRHEA_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_PRIVRHEA_PSA_HSB
//-------------------
#define TESTBLOCK_PRIVRHEA_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_PRIVRHEA_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_PRIVRHEA_PSA_HSB_PRIVRHEA_HSB_POS 0
#define TESTBLOCK_PRIVRHEA_PSA_HSB_PRIVRHEA_HSB_NUMB 20
#define TESTBLOCK_PRIVRHEA_PSA_HSB_PRIVRHEA_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_OCPT1_PSA_LSB
//-------------------
#define TESTBLOCK_OCPT1_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPT1_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_OCPT1_PSA_LSB_OCPT1_LSB_POS 0
#define TESTBLOCK_OCPT1_PSA_LSB_OCPT1_LSB_NUMB 20
#define TESTBLOCK_OCPT1_PSA_LSB_OCPT1_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_OCPT1_PSA_HSB
//-------------------
#define TESTBLOCK_OCPT1_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPT1_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_OCPT1_PSA_HSB_OCPT1_HSB_POS 0
#define TESTBLOCK_OCPT1_PSA_HSB_OCPT1_HSB_NUMB 20
#define TESTBLOCK_OCPT1_PSA_HSB_OCPT1_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_OCPT2_PSA_LSB
//-------------------
#define TESTBLOCK_OCPT2_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPT2_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_OCPT2_PSA_LSB_OCPT2_LSB_POS 0
#define TESTBLOCK_OCPT2_PSA_LSB_OCPT2_LSB_NUMB 20
#define TESTBLOCK_OCPT2_PSA_LSB_OCPT2_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_OCPT2_PSA_HSB
//-------------------
#define TESTBLOCK_OCPT2_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPT2_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_OCPT2_PSA_HSB_OCPT2_HSB_POS 0
#define TESTBLOCK_OCPT2_PSA_HSB_OCPT2_HSB_NUMB 20
#define TESTBLOCK_OCPT2_PSA_HSB_OCPT2_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_OCPI_PSA_LSB
//-------------------
#define TESTBLOCK_OCPI_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPI_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_OCPI_PSA_LSB_OCPI_LSB_POS 0
#define TESTBLOCK_OCPI_PSA_LSB_OCPI_LSB_NUMB 20
#define TESTBLOCK_OCPI_PSA_LSB_OCPI_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_OCPI_PSA_HSB
//-------------------
#define TESTBLOCK_OCPI_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPI_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_OCPI_PSA_HSB_OCPI_HSB_POS 0
#define TESTBLOCK_OCPI_PSA_HSB_OCPI_HSB_NUMB 20
#define TESTBLOCK_OCPI_PSA_HSB_OCPI_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_LCD_PSA
//-------------------
#define TESTBLOCK_LCD_PSA REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_LCD_PSA_OFFSET)
//R
#define TESTBLOCK_LCD_PSA_LCD_PSA_POS 0
#define TESTBLOCK_LCD_PSA_LCD_PSA_NUMB 20
#define TESTBLOCK_LCD_PSA_LCD_PSA_RES_VAL 0x00000
//R
//TESTBLOCK_EXLCD_PSA
//-------------------
#define TESTBLOCK_EXLCD_PSA REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_EXLCD_PSA_OFFSET)
//R
#define TESTBLOCK_EXLCD_PSA_EXLCD_PSA_POS 0
#define TESTBLOCK_EXLCD_PSA_EXLCD_PSA_NUMB 20
#define TESTBLOCK_EXLCD_PSA_EXLCD_PSA_RES_VAL 0x00000
//R
//TESTBLOCK_SECURITY_REG
//-------------------
#define TESTBLOCK_SECURITY_REG REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_SECURITY_REG_OFFSET)
//R
#define TESTBLOCK_SECURITY_REG_SEC_AT_SPEED_MODE_POS 6
#define TESTBLOCK_SECURITY_REG_SEC_AT_SPEED_MODE_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_AT_SPEED_MODE_RES_VAL 0x0
//R
#define TESTBLOCK_SECURITY_REG_SEC_TEST_MODE_POS 5
#define TESTBLOCK_SECURITY_REG_SEC_TEST_MODE_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_TEST_MODE_RES_VAL 0x0
//R
#define TESTBLOCK_SECURITY_REG_SEC_IT_MASK_POS 4
#define TESTBLOCK_SECURITY_REG_SEC_IT_MASK_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_IT_MASK_RES_VAL 0x0
//R
#define TESTBLOCK_SECURITY_REG_SEC_ETM_IF_EN_POS 3
#define TESTBLOCK_SECURITY_REG_SEC_ETM_IF_EN_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_ETM_IF_EN_RES_VAL 0x1
//R/W
#define TESTBLOCK_SECURITY_REG_SEC_OCPI_BLOCK_POS 2
#define TESTBLOCK_SECURITY_REG_SEC_OCPI_BLOCK_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_OCPI_BLOCK_RES_VAL 0x1
//R/W
#define TESTBLOCK_SECURITY_REG_SEC_DMA_BLOCK_POS 1
#define TESTBLOCK_SECURITY_REG_SEC_DMA_BLOCK_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_DMA_BLOCK_RES_VAL 0x0
//R/W
#define TESTBLOCK_SECURITY_REG_SEC_TRACE_DIS_POS 0
#define TESTBLOCK_SECURITY_REG_SEC_TRACE_DIS_NUMB 1
#define TESTBLOCK_SECURITY_REG_SEC_TRACE_DIS_RES_VAL 0x1
//R/W
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -