📄 omap_32_testblock.h
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//R/W
#define TESTBLOCK_TMCR1_PUB_RHEA_PSA_RESET_POS 4
#define TESTBLOCK_TMCR1_PUB_RHEA_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_PUB_RHEA_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_EMIFF_PSA_ON_POS 3
#define TESTBLOCK_TMCR1_EMIFF_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_EMIFF_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_EMIFF_PSA_RESET_POS 2
#define TESTBLOCK_TMCR1_EMIFF_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_EMIFF_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_EMIFS_PSA_ON_POS 1
#define TESTBLOCK_TMCR1_EMIFS_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_EMIFS_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_EMIFS_PSA_RESET_POS 0
#define TESTBLOCK_TMCR1_EMIFS_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_EMIFS_PSA_RESET_RES_VAL 0x0
//R/W
//TESTBLOCK_AINTR_FB_REG_0
//-------------------
#define TESTBLOCK_AINTR_FB_REG_0 REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_AINTR_FB_REG_0_OFFSET)
#define TESTBLOCK_AINTR_FB_REG_0_FB_IRQINPUT_31TO1_POS 1
#define TESTBLOCK_AINTR_FB_REG_0_FB_IRQINPUT_31TO1_NUMB 31
#define TESTBLOCK_AINTR_FB_REG_0_FB_IRQINPUT_31TO1_RES_VAL 0x7FFFFFFF
//R/W
#define TESTBLOCK_AINTR_FB_REG_0_FB_ARMABORTN_POS 0
#define TESTBLOCK_AINTR_FB_REG_0_FB_ARMABORTN_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_0_FB_ARMABORTN_RES_VAL 0x1
//R/W
//TESTBLOCK_AINTR_FB_REG_1
//-------------------
#define TESTBLOCK_AINTR_FB_REG_1 REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_AINTR_FB_REG_1_OFFSET)
//R
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_EN_POS 8
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_EN_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_EN_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG7_POS 7
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG7_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG7_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG6_POS 6
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG6_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG6_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG5_POS 5
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG5_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG5_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG4_POS 4
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG4_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG4_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG3_POS 3
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG3_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG3_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG2_POS 2
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG2_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG2_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG1_POS 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG1_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG1_RES_VAL 0x0
//W
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG0_POS 0
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG0_NUMB 1
#define TESTBLOCK_AINTR_FB_REG_1_SHIFT_REG0_RES_VAL 0x0
//W
//TESTBLOCK_DINTR_FB_REG
//-------------------
#define TESTBLOCK_DINTR_FB_REG REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_DINTR_FB_REG_OFFSET)
//R
#define TESTBLOCK_DINTR_FB_REG_SHIFT_EN_POS 24
#define TESTBLOCK_DINTR_FB_REG_SHIFT_EN_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_EN_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG7_POS 23
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG7_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG7_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG6_POS 22
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG6_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG6_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG5_POS 21
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG5_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG5_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG4_POS 20
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG4_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG4_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG3_POS 19
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG3_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG3_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG2_POS 18
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG2_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG2_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG1_POS 17
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG1_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG1_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG0_POS 16
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG0_NUMB 1
#define TESTBLOCK_DINTR_FB_REG_SHIFT_REG0_RES_VAL 0x0
//W
#define TESTBLOCK_DINTR_FB_REG_FB_DSPL2INTN_15TO0_POS 0
#define TESTBLOCK_DINTR_FB_REG_FB_DSPL2INTN_15TO0_NUMB 16
#define TESTBLOCK_DINTR_FB_REG_FB_DSPL2INTN_15TO0_RES_VAL 0xFFFF
//R/W
//TESTBLOCK_DMA_REQ_FB_REG
//-------------------
#define TESTBLOCK_DMA_REQ_FB_REG REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_DMA_REQ_FB_REG_OFFSET)
#define TESTBLOCK_DMA_REQ_FB_REG_FB_DMAREQEDGEN_POS 31
#define TESTBLOCK_DMA_REQ_FB_REG_FB_DMAREQEDGEN_NUMB 1
#define TESTBLOCK_DMA_REQ_FB_REG_FB_DMAREQEDGEN_RES_VAL 0x1
//R/W
#define TESTBLOCK_DMA_REQ_FB_REG_FB_DMAREQN_30TO0_POS 0
#define TESTBLOCK_DMA_REQ_FB_REG_FB_DMAREQN_30TO0_NUMB 31
#define TESTBLOCK_DMA_REQ_FB_REG_FB_DMAREQN_30TO0_RES_VAL 0x7FFFFFFF
//R/W
//TESTBLOCK_OCPI_TOPAD_REG
//-------------------
#define TESTBLOCK_OCPI_TOPAD_REG REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OCPI_TOPAD_REG_OFFSET)
//R
#define TESTBLOCK_OCPI_TOPAD_REG_OCPI_TOPAD_POS 0
#define TESTBLOCK_OCPI_TOPAD_REG_OCPI_TOPAD_NUMB 4
#define TESTBLOCK_OCPI_TOPAD_REG_OCPI_TOPAD_RES_VAL 0x2
//R/W
//TESTBLOCK_EMIFS_PSA_LSB
//-------------------
#define TESTBLOCK_EMIFS_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_EMIFS_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_EMIFS_PSA_LSB_EMIFS_LSB_POS 0
#define TESTBLOCK_EMIFS_PSA_LSB_EMIFS_LSB_NUMB 20
#define TESTBLOCK_EMIFS_PSA_LSB_EMIFS_LSB_RES_VAL 0x00000
//R
//TESTBLOCK_EMIFS_PSA_HSB
//-------------------
#define TESTBLOCK_EMIFS_PSA_HSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_EMIFS_PSA_HSB_OFFSET)
//R
#define TESTBLOCK_EMIFS_PSA_HSB_EMIFS_HSB_POS 0
#define TESTBLOCK_EMIFS_PSA_HSB_EMIFS_HSB_NUMB 20
#define TESTBLOCK_EMIFS_PSA_HSB_EMIFS_HSB_RES_VAL 0x00000
//R
//TESTBLOCK_EMIFF_PSA_LSB
//-------------------
#define TESTBLOCK_EMIFF_PSA_LSB REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_EMIFF_PSA_LSB_OFFSET)
//R
#define TESTBLOCK_EMIFF_PSA_LSB_EMIFF_LSB_POS 0
#define TESTBLOCK_EMIFF_PSA_LSB_EMIFF_LSB_NUMB 20
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