📄 omap_32_testblock.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :omap_32_testblock.h
//
// Date of Module Modification:4/25/02
// Date of Generation :5/3/02
//
//
//========================================================================
#include "omap_32_mapping.h"
#ifndef _TESTBLOCK__H
#define _TESTBLOCK__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define TESTBLOCK_OMAP_ID_REG_OFFSET 0x00
#define TESTBLOCK_OMAP_USER_ID_REG_OFFSET 0x04
#define TESTBLOCK_TMCR0_OFFSET 0x08
#define TESTBLOCK_TMCR1_OFFSET 0x0C
#define TESTBLOCK_AINTR_FB_REG_0_OFFSET 0x10
#define TESTBLOCK_AINTR_FB_REG_1_OFFSET 0x14
#define TESTBLOCK_DINTR_FB_REG_OFFSET 0x18
#define TESTBLOCK_DMA_REQ_FB_REG_OFFSET 0x1c
#define TESTBLOCK_OCPI_TOPAD_REG_OFFSET 0x20
#define TESTBLOCK_EMIFS_PSA_LSB_OFFSET 0x30
#define TESTBLOCK_EMIFS_PSA_HSB_OFFSET 0x34
#define TESTBLOCK_EMIFF_PSA_LSB_OFFSET 0x38
#define TESTBLOCK_EMIFF_PSA_HSB_OFFSET 0x3C
#define TESTBLOCK_PUBRHEA_PSA_LSB_OFFSET 0x40
#define TESTBLOCK_PUBRHEA_PSA_HSB_OFFSET 0x44
#define TESTBLOCK_PRIVRHEA_PSA_LSB_OFFSET 0x48
#define TESTBLOCK_PRIVRHEA_PSA_HSB_OFFSET 0x4C
#define TESTBLOCK_OCPT1_PSA_LSB_OFFSET 0x50
#define TESTBLOCK_OCPT1_PSA_HSB_OFFSET 0x54
#define TESTBLOCK_OCPT2_PSA_LSB_OFFSET 0x58
#define TESTBLOCK_OCPT2_PSA_HSB_OFFSET 0x5C
#define TESTBLOCK_OCPI_PSA_LSB_OFFSET 0x60
#define TESTBLOCK_OCPI_PSA_HSB_OFFSET 0x64
#define TESTBLOCK_LCD_PSA_OFFSET 0x68
#define TESTBLOCK_EXLCD_PSA_OFFSET 0x6C
#define TESTBLOCK_SECURITY_REG_OFFSET 0x80
//TESTBLOCK_OMAP_ID_REG
//-------------------
#define TESTBLOCK_OMAP_ID_REG REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OMAP_ID_REG_OFFSET)
#define TESTBLOCK_OMAP_ID_REG_OMAP_ID_REG_POS 0
#define TESTBLOCK_OMAP_ID_REG_OMAP_ID_REG_NUMB 32
#define TESTBLOCK_OMAP_ID_REG_OMAP_ID_REG_RES_VAL 0x03320000
//R
//TESTBLOCK_OMAP_USER_ID_REG
//-------------------
#define TESTBLOCK_OMAP_USER_ID_REG REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_OMAP_USER_ID_REG_OFFSET)
#define TESTBLOCK_OMAP_USER_ID_REG_USER_ID_POS 0
#define TESTBLOCK_OMAP_USER_ID_REG_USER_ID_NUMB 32
#define TESTBLOCK_OMAP_USER_ID_REG_USER_ID_RES_VAL 0xA5A55A5A
//R
//TESTBLOCK_TMCR0
//-------------------
#define TESTBLOCK_TMCR0 REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_TMCR0_OFFSET)
//R
#define TESTBLOCK_TMCR0_EXLCDDMAREQ_POS 16
#define TESTBLOCK_TMCR0_EXLCDDMAREQ_NUMB 1
#define TESTBLOCK_TMCR0_EXLCDDMAREQ_RES_VAL 0x1
//R/W
#define TESTBLOCK_TMCR0_GL_MEMSEL_TR_POS 14
#define TESTBLOCK_TMCR0_GL_MEMSEL_TR_NUMB 2
#define TESTBLOCK_TMCR0_GL_MEMSEL_TR_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_GL_MEMTEST_TR_POS 13
#define TESTBLOCK_TMCR0_GL_MEMTEST_TR_NUMB 1
#define TESTBLOCK_TMCR0_GL_MEMTEST_TR_RES_VAL 0x0
//R/W
//R
#define TESTBLOCK_TMCR0_OCPTI_LPBK_ON_POS 8
#define TESTBLOCK_TMCR0_OCPTI_LPBK_ON_NUMB 1
#define TESTBLOCK_TMCR0_OCPTI_LPBK_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_OCPT2_FDBK_ON_POS 7
#define TESTBLOCK_TMCR0_OCPT2_FDBK_ON_NUMB 1
#define TESTBLOCK_TMCR0_OCPT2_FDBK_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_OCPT1_FDBK_ON_POS 6
#define TESTBLOCK_TMCR0_OCPT1_FDBK_ON_NUMB 1
#define TESTBLOCK_TMCR0_OCPT1_FDBK_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_DINTR_FDBK_OFF_POS 5
#define TESTBLOCK_TMCR0_DINTR_FDBK_OFF_NUMB 1
#define TESTBLOCK_TMCR0_DINTR_FDBK_OFF_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_AINTR_FDBK_LPBK_POS 4
#define TESTBLOCK_TMCR0_AINTR_FDBK_LPBK_NUMB 1
#define TESTBLOCK_TMCR0_AINTR_FDBK_LPBK_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_AINTR_FDBK_OFF_POS 3
#define TESTBLOCK_TMCR0_AINTR_FDBK_OFF_NUMB 1
#define TESTBLOCK_TMCR0_AINTR_FDBK_OFF_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_RHEA_FDBK_OFF_POS 2
#define TESTBLOCK_TMCR0_RHEA_FDBK_OFF_NUMB 1
#define TESTBLOCK_TMCR0_RHEA_FDBK_OFF_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_EMIFS_FDBK_ON_POS 1
#define TESTBLOCK_TMCR0_EMIFS_FDBK_ON_NUMB 1
#define TESTBLOCK_TMCR0_EMIFS_FDBK_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR0_OMAP_FDBK_ON_POS 0
#define TESTBLOCK_TMCR0_OMAP_FDBK_ON_NUMB 1
#define TESTBLOCK_TMCR0_OMAP_FDBK_ON_RES_VAL 0x0
//R/W
//TESTBLOCK_TMCR1
//-------------------
#define TESTBLOCK_TMCR1 REG32(TESTBLOCK_BASE_ADDR_ARM+TESTBLOCK_TMCR1_OFFSET)
//R
#define TESTBLOCK_TMCR1_EXTLCD_PSA_ON_POS 17
#define TESTBLOCK_TMCR1_EXTLCD_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_EXTLCD_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_EXTLCD_PSA_RESET_POS 16
#define TESTBLOCK_TMCR1_EXTLCD_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_EXTLCD_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_LCD_PSA_ON_POS 15
#define TESTBLOCK_TMCR1_LCD_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_LCD_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_LCD_PSA_RESET_POS 14
#define TESTBLOCK_TMCR1_LCD_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_LCD_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_OCPI_PSA_ON_POS 13
#define TESTBLOCK_TMCR1_OCPI_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_OCPI_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_OCPI_PSA_RESET_POS 12
#define TESTBLOCK_TMCR1_OCPI_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_OCPI_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_OCPT2_PSA_ON_POS 11
#define TESTBLOCK_TMCR1_OCPT2_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_OCPT2_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_OCPT2_PSA_RESET_POS 10
#define TESTBLOCK_TMCR1_OCPT2_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_OCPT2_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_OCPT1_PSA_ON_POS 9
#define TESTBLOCK_TMCR1_OCPT1_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_OCPT1_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_OCPT1_PSA_RESET_POS 8
#define TESTBLOCK_TMCR1_OCPT1_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_OCPT1_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_PRIV_RHEA_PSA_ON_POS 7
#define TESTBLOCK_TMCR1_PRIV_RHEA_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_PRIV_RHEA_PSA_ON_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_PRIV_RHEA_PSA_RESET_POS 6
#define TESTBLOCK_TMCR1_PRIV_RHEA_PSA_RESET_NUMB 1
#define TESTBLOCK_TMCR1_PRIV_RHEA_PSA_RESET_RES_VAL 0x0
//R/W
#define TESTBLOCK_TMCR1_PUB_RHEA_PSA_ON_POS 5
#define TESTBLOCK_TMCR1_PUB_RHEA_PSA_ON_NUMB 1
#define TESTBLOCK_TMCR1_PUB_RHEA_PSA_ON_RES_VAL 0x0
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