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📄 mcbsp_rf.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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/*Header modified by DSP-CONVERT V1.01 Script on  Tue Aug 13 14:51:43 MEST 2002*/
//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :mcbsp2.h
//
//   Date of Module Modification:5/29/02
//   Date of Generation :6/19/02
//
//
//========================================================================
#ifndef _MCBSP_DIGITAL_RF__H
#define _MCBSP_DIGITAL_RF__H

#include "mapping.h"
#include "global_types.h"
#include "clkrst.h"
#include "reset.h"
#include "mcbsp.h"
#include "errorcodes.h"

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            MCBSP_DIGITAL_RF_MCBSP_DRR2_REG_OFFSET            0x00
#define            MCBSP_DIGITAL_RF_MCBSP_DRR1_REG_OFFSET            0x02
#define            MCBSP_DIGITAL_RF_MCBSP_DXR2_REG_OFFSET            0x04
#define            MCBSP_DIGITAL_RF_MCBSP_DXR1_REG_OFFSET            0x06
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_OFFSET           0x08
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_OFFSET           0x0A
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_OFFSET            0x0C
#define            MCBSP_DIGITAL_RF_MCBSP_RCR1_REG_OFFSET            0x0E
#define            MCBSP_DIGITAL_RF_MCBSP_XCR2_REG_OFFSET            0x10
#define            MCBSP_DIGITAL_RF_MCBSP_XCR1_REG_OFFSET            0x12
#define            MCBSP_DIGITAL_RF_MCBSP_SRGR2_REG_OFFSET           0x14
#define            MCBSP_DIGITAL_RF_MCBSP_SRGR1_REG_OFFSET           0x16
#define            MCBSP_DIGITAL_RF_MCBSP_MCR2_REG_OFFSET            0x18
#define            MCBSP_DIGITAL_RF_MCBSP_MCR1_REG_OFFSET            0x1A
#define            MCBSP_DIGITAL_RF_MCBSP_RCERA_REG_OFFSET           0x1C
#define            MCBSP_DIGITAL_RF_MCBSP_RCERB_REG_OFFSET           0x1E
#define            MCBSP_DIGITAL_RF_MCBSP_XCERA_REG_OFFSET           0x20
#define            MCBSP_DIGITAL_RF_MCBSP_XCERB_REG_OFFSET           0x22
#define            MCBSP_DIGITAL_RF_MCBSP_PCR_REG_OFFSET             0x24
#define            MCBSP_DIGITAL_RF_MCBSP_RCERC_REG_OFFSET           0x26
#define            MCBSP_DIGITAL_RF_MCBSP_RCERD_REG_OFFSET           0x28
#define            MCBSP_DIGITAL_RF_MCBSP_XCERC_REG_OFFSET           0x2A
#define            MCBSP_DIGITAL_RF_MCBSP_XCERD_REG_OFFSET           0x2C
#define            MCBSP_DIGITAL_RF_MCBSP_RCERE_REG_OFFSET           0x2E
#define            MCBSP_DIGITAL_RF_MCBSP_RCERF_REG_OFFSET           0x30
#define            MCBSP_DIGITAL_RF_MCBSP_XCERE_REG_OFFSET           0x32
#define            MCBSP_DIGITAL_RF_MCBSP_XCERF_REG_OFFSET           0x34
#define            MCBSP_DIGITAL_RF_MCBSP_RCERG_REG_OFFSET           0x36
#define            MCBSP_DIGITAL_RF_MCBSP_RCERH_REG_OFFSET           0x38
#define            MCBSP_DIGITAL_RF_MCBSP_XCERG_REG_OFFSET           0x3A
#define            MCBSP_DIGITAL_RF_MCBSP_XCERH_REG_OFFSET           0x3C
#define            MCBSP_DIGITAL_RF_MCBSP_REV_REG_OFFSET             0x3E



//MCBSP_DIGITAL_RF_MCBSP_DRR2_REG
#define            MCBSP_DIGITAL_RF_MCBSP_DRR2_REG                   REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_DRR2_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_DRR2_REG_DRR2_POS            0
#define            MCBSP_DIGITAL_RF_MCBSP_DRR2_REG_DRR2_NUMB           16
#define            MCBSP_DIGITAL_RF_MCBSP_DRR2_REG_DRR2_RES_VAL        none
//R


//MCBSP_DIGITAL_RF_MCBSP_DRR1_REG
#define            MCBSP_DIGITAL_RF_MCBSP_DRR1_REG                   REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_DRR1_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_DRR1_REG_DRR1_POS            0
#define            MCBSP_DIGITAL_RF_MCBSP_DRR1_REG_DRR1_NUMB           16
#define            MCBSP_DIGITAL_RF_MCBSP_DRR1_REG_DRR1_RES_VAL        none
//R


//MCBSP_DIGITAL_RF_MCBSP_DXR2_REG
#define            MCBSP_DIGITAL_RF_MCBSP_DXR2_REG                   REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_DXR2_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_DXR2_REG_DXR2_POS            0
#define            MCBSP_DIGITAL_RF_MCBSP_DXR2_REG_DXR2_NUMB           16
#define            MCBSP_DIGITAL_RF_MCBSP_DXR2_REG_DXR2_RES_VAL        none
//W


//MCBSP_DIGITAL_RF_MCBSP_DXR1_REG
#define            MCBSP_DIGITAL_RF_MCBSP_DXR1_REG                   REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_DXR1_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_DXR1_REG_DXR1_POS            0
#define            MCBSP_DIGITAL_RF_MCBSP_DXR1_REG_DXR1_NUMB           16
#define            MCBSP_DIGITAL_RF_MCBSP_DXR1_REG_DXR1_RES_VAL        none
//W


//MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG                  REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_RSVD_POS           10
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_RSVD_NUMB          6
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_RSVD_RES_VAL       0x0
//R

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_FREE_POS           9
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_FREE_NUMB          1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_FREE_RES_VAL       0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_SOFT_POS           8
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_SOFT_NUMB          1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_SOFT_RES_VAL       0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_FRST__POS          7
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_FRST__NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_FRST__RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_GRST__POS          6
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_GRST__NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_GRST__RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XINTM_POS          4
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XINTM_NUMB         2
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XINTM_RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XSYNCERR_POS       3
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XSYNCERR_NUMB      1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XSYNCERR_RES_VAL   0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XEMPTY__POS        2
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XEMPTY__NUMB       1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XEMPTY__RES_VAL    0x0
//R

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XRDY_POS           1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XRDY_NUMB          1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XRDY_RES_VAL       0x0
//R

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XRST__POS          0
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XRST__NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR2_REG_XRST__RES_VAL      0x0
//R/W


//MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG                  REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_DLB_POS            15
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_DLB_NUMB           1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_DLB_RES_VAL        0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RJUST_POS          13
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RJUST_NUMB         2
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RJUST_RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_CLKSTP_POS         11
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_CLKSTP_NUMB        2
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_CLKSTP_RES_VAL     0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RSVD_POS           8
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RSVD_NUMB          3
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RSVD_RES_VAL       0x0
//R

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_DXENA_POS          7
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_DXENA_NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_DXENA_RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_ABIS_POS           6
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_ABIS_NUMB          1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_ABIS_RES_VAL       0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RINTM_POS          4
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RINTM_NUMB         2
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RINTM_RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RSYNCERR_POS       3
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RSYNCERR_NUMB      1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RSYNCERR_RES_VAL   0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RFULL_POS          2
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RFULL_NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RFULL_RES_VAL      0x0
//R

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RRDY_POS           1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RRDY_NUMB          1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RRDY_RES_VAL       0x0
//R

#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RRST__POS          0
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RRST__NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_SPCR1_REG_RRST__RES_VAL      0x0
//R/W


//MCBSP_DIGITAL_RF_MCBSP_RCR2_REG
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG                   REG16(MCBSP_DIGITAL_RF_BASE_ADDR_ARM+MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_OFFSET)

#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RPHASE_POS          15
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RPHASE_NUMB         1
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RPHASE_RES_VAL      0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RFRLEN2_POS         8
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RFRLEN2_NUMB        7
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RFRLEN2_RES_VAL     0x0
//R/W

#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RWDLEN2_POS         5
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RWDLEN2_NUMB        3
#define            MCBSP_DIGITAL_RF_MCBSP_RCR2_REG_RWDLEN2_RES_VAL     0x0
//R/W

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