📄 pcc_ulpd.h
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#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL_POS 2
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL_NUMB 6
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL_RES_VAL 0x0
//R/W
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_POS 1
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_NUMB 1
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_POS 0
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_NUMB 1
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_RES_VAL 0x1
//R/W
//PCC_ULPD_COM_CLK_DIV_CTRL_SEL
//-------------------
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_COM_CLK_DIV_CTRL_SEL_OFFSET)
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL_POS 2
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL_NUMB 6
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL_RES_VAL 0x0
//R/W
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_POS 1
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_NUMB 1
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_POS 0
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_NUMB 1
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_RES_VAL 0x1
//R/W
//PCC_ULPD_CAM_CLK_CTRL
//-------------------
#define PCC_ULPD_CAM_CLK_CTRL REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_CAM_CLK_CTRL_OFFSET)
#define PCC_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_POS 2
#define PCC_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_NUMB 1
#define PCC_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_RES_VAL 0x0
//R/W
#define PCC_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_POS 1
#define PCC_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_NUMB 1
#define PCC_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_RES_VAL 0x0
//R/W
#define PCC_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_POS 0
#define PCC_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_NUMB 1
#define PCC_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_RES_VAL 0x0
//R/W
//PCC_ULPD_SOFT_REQ_REG2
//-------------------
#define PCC_ULPD_SOFT_REQ_REG2 REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SOFT_REQ_REG2_OFFSET)
#define PCC_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_POS 0
#define PCC_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_RES_VAL 0X0
//R/W
//PCC_ULPD_PCC_CTRL_REG
//-------------------
#define PCC_ULPD_PCC_CTRL_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_PCC_CTRL_REG_OFFSET)
#define PCC_ULPD_PCC_CTRL_REG_RESERVED_POS 15
#define PCC_ULPD_PCC_CTRL_REG_RESERVED_NUMB -8
#define PCC_ULPD_PCC_CTRL_REG_RESERVED_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_CTRL_REG_SYERN_CLK_SWITCH_STS_POS 5
#define PCC_ULPD_PCC_CTRL_REG_SYERN_CLK_SWITCH_STS_NUMB 1
#define PCC_ULPD_PCC_CTRL_REG_SYERN_CLK_SWITCH_STS_RES_VAL 0x1
//R
#define PCC_ULPD_PCC_CTRL_REG_APLL96_INPUT_SWITCH_STS_POS 4
#define PCC_ULPD_PCC_CTRL_REG_APLL96_INPUT_SWITCH_STS_NUMB 1
#define PCC_ULPD_PCC_CTRL_REG_APLL96_INPUT_SWITCH_STS_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_CTRL_REG_ULPD_INPUT_SWITCH_STS_POS 3
#define PCC_ULPD_PCC_CTRL_REG_ULPD_INPUT_SWITCH_STS_NUMB 1
#define PCC_ULPD_PCC_CTRL_REG_ULPD_INPUT_SWITCH_STS_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_CTRL_REG_SLC_OUT_DIV_POS 2
#define PCC_ULPD_PCC_CTRL_REG_SLC_OUT_DIV_NUMB 1
#define PCC_ULPD_PCC_CTRL_REG_SLC_OUT_DIV_RES_VAL 0x1
//R/W
#define PCC_ULPD_PCC_CTRL_REG_APLL_ALWAYS_ON_POS 1
#define PCC_ULPD_PCC_CTRL_REG_APLL_ALWAYS_ON_NUMB 1
#define PCC_ULPD_PCC_CTRL_REG_APLL_ALWAYS_ON_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_CTRL_REG_CLK_SWITCH_CMD_POS 0
#define PCC_ULPD_PCC_CTRL_REG_CLK_SWITCH_CMD_NUMB 1
#define PCC_ULPD_PCC_CTRL_REG_CLK_SWITCH_CMD_RES_VAL 0x0
//R/W
//PCC_ULPD_PCC_POWER_CTRL_REG
//-------------------
#define PCC_ULPD_PCC_POWER_CTRL_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_PCC_POWER_CTRL_REG_OFFSET)
#define PCC_ULPD_PCC_POWER_CTRL_REG_RESERVED_POS 10
#define PCC_ULPD_PCC_POWER_CTRL_REG_RESERVED_NUMB 6
#define PCC_ULPD_PCC_POWER_CTRL_REG_RESERVED_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_POWER_CTRL_REG_DIS_DBB32K_CLK_POS 9
#define PCC_ULPD_PCC_POWER_CTRL_REG_DIS_DBB32K_CLK_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_DIS_DBB32K_CLK_RES_VAL 0x1
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_OSC_32K_BYPASS_POS 8
#define PCC_ULPD_PCC_POWER_CTRL_REG_OSC_32K_BYPASS_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_OSC_32K_BYPASS_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_DIS_RF_EN_POS 7
#define PCC_ULPD_PCC_POWER_CTRL_REG_DIS_RF_EN_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_DIS_RF_EN_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_ENABLE_SOFT_DRIVE_POS 6
#define PCC_ULPD_PCC_POWER_CTRL_REG_ENABLE_SOFT_DRIVE_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_ENABLE_SOFT_DRIVE_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_PWRDN_POS 5
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_PWRDN_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_PWRDN_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_SLEEP_POS 4
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_SLEEP_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_SLEEP_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_STEADY_POS 3
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_STEADY_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_MPU_LDO_STEADY_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_PWRDN_POS 2
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_PWRDN_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_PWRDN_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_SLEEP_POS 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_SLEEP_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_SLEEP_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_STEADY_POS 0
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_STEADY_NUMB 1
#define PCC_ULPD_PCC_POWER_CTRL_REG_DBB_LDO_STEADY_RES_VAL 0x0
//R
//PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL
//-------------------
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_OFFSET)
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_RESERVED_POS 10
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_RESERVED_NUMB 6
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_RESERVED_RES_VAL 0x0
//R
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_SYREN_PERIPH_CLK_POS 9
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_SYREN_PERIPH_CLK_NUMB 1
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_SYREN_PERIPH_CLK_RES_VAL 0x0
//R/W
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_RESERVED2_POS 8
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_RESERVE⌨️ 快捷键说明
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