📄 pcc_ulpd.h
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#define PCC_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RES_VAL 0x1
//R/W
#define PCC_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RST_POS 2
#define PCC_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RST_NUMB 1
#define PCC_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RST_RES_VAL 0x0
//R/W
#define PCC_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_POS 1
#define PCC_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_NUMB 1
#define PCC_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_POWER_CTRL_REG_LOW_PWR_EN_POS 0
#define PCC_ULPD_POWER_CTRL_REG_LOW_PWR_EN_NUMB 1
#define PCC_ULPD_POWER_CTRL_REG_LOW_PWR_EN_RES_VAL 0x0
//R/W
//PCC_ULPD_STATUS_REQ_REG2
//-------------------
#define PCC_ULPD_STATUS_REQ_REG2 REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_STATUS_REQ_REG2_OFFSET)
#define PCC_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_POS 0
#define PCC_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_NUMB 1
#define PCC_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_RES_VAL UNKNOWN
//R
//PCC_ULPD_SLEEP_STATUS
//-------------------
#define PCC_ULPD_SLEEP_STATUS REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SLEEP_STATUS_OFFSET)
#define PCC_ULPD_SLEEP_STATUS_BIG_SLEEP_POS 1
#define PCC_ULPD_SLEEP_STATUS_BIG_SLEEP_NUMB 1
#define PCC_ULPD_SLEEP_STATUS_BIG_SLEEP_RES_VAL UNKNOWN
//R
#define PCC_ULPD_SLEEP_STATUS_DEEP_SLEEP_POS 0
#define PCC_ULPD_SLEEP_STATUS_DEEP_SLEEP_NUMB 1
#define PCC_ULPD_SLEEP_STATUS_DEEP_SLEEP_RES_VAL UNKNOWN
//R
//PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG
//-------------------
#define PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG_OFFSET)
#define PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG_SETUP_ANALOG_CELL4_POS 0
#define PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG_SETUP_ANALOG_CELL4_NUMB 16
#define PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG_SETUP_ANALOG_CELL4_RES_VAL 0x0
//R/W
//PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG
//-------------------
#define PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG_OFFSET)
#define PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG_SETUP_ANALOG_CELL5_POS 0
#define PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG_SETUP_ANALOG_CELL5_NUMB 16
#define PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG_SETUP_ANALOG_CELL5_RES_VAL 0x0
//R/W
//PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG
//-------------------
#define PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG_OFFSET)
#define PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG_SETUP_ANALOG_CELL6_POS 0
#define PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG_SETUP_ANALOG_CELL6_NUMB 16
#define PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG_SETUP_ANALOG_CELL6_RES_VAL 0x0
//R/W
//PCC_ULPD_SOFT_DISABLE_REQ_REG
//-------------------
#define PCC_ULPD_SOFT_DISABLE_REQ_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SOFT_DISABLE_REQ_REG_OFFSET)
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_POS 14
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_POS 13
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_POS 12
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_POS 11
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_POS 10
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_POS 9
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_POS 8
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_POS 7
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_POS 6
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_POS 5
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_POS 3
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_POS 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_POS 0
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_NUMB 1
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_RES_VAL 0x0
//R/W
//PCC_ULPD_RESET_STATUS
//-------------------
#define PCC_ULPD_RESET_STATUS REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_RESET_STATUS_OFFSET)
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_3_POS 3
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_3_NUMB 1
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_3_RES_VAL 0x0
//R/W
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_2_POS 2
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_2_NUMB 1
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_2_RES_VAL 0x0
//R/W
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_1_POS 1
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_1_NUMB 1
#define PCC_ULPD_RESET_STATUS_EXTERNAL_RESET_SOURCE_1_RES_VAL 0x0
//R/W
#define PCC_ULPD_RESET_STATUS_POWER_ON_RESET_POS 0
#define PCC_ULPD_RESET_STATUS_POWER_ON_RESET_NUMB 1
#define PCC_ULPD_RESET_STATUS_POWER_ON_RESET_RES_VAL 0x1
//R/W
//PCC_ULPD_REVISION_NUMBER
//-------------------
#define PCC_ULPD_REVISION_NUMBER REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_REVISION_NUMBER_OFFSET)
#define PCC_ULPD_REVISION_NUMBER_REVISION_NUMBER_POS 0
#define PCC_ULPD_REVISION_NUMBER_REVISION_NUMBER_NUMB 8
#define PCC_ULPD_REVISION_NUMBER_REVISION_NUMBER_RES_VAL 0x11
//R
//PCC_ULPD_SDW_CLK_DIV_CTRL_SEL
//-------------------
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_OFFSET)
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