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📄 pcc_ulpd.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#define            PCC_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_NUMB                                                          1
#define            PCC_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_RES_VAL                                                       UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_POS                                                           14
#define            PCC_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_NUMB                                                          1
#define            PCC_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_RES_VAL                                                       UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_POS                                                           13
#define            PCC_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_NUMB                                                          1
#define            PCC_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_RES_VAL                                                       UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_POS                                                              12
#define            PCC_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_NUMB                                                             1
#define            PCC_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_RES_VAL                                                          UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_POS                                                            11
#define            PCC_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_NUMB                                                           1
#define            PCC_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_RES_VAL                                                        UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_POS                                                            10
#define            PCC_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_NUMB                                                           1
#define            PCC_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_RES_VAL                                                        UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_POS                                                            9
#define            PCC_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_NUMB                                                           1
#define            PCC_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_RES_VAL                                                        UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_POS                                                         8
#define            PCC_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_NUMB                                                        1
#define            PCC_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_RES_VAL                                                     UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_POS                                                         7
#define            PCC_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_NUMB                                                        1
#define            PCC_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_RES_VAL                                                     UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_POS                                                         6
#define            PCC_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_NUMB                                                        1
#define            PCC_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_RES_VAL                                                     UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_POS                                                              5
#define            PCC_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_NUMB                                                             1
#define            PCC_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_RES_VAL                                                          UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_POS                                                              4
#define            PCC_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_NUMB                                                             1
#define            PCC_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_RES_VAL                                                          UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_POS                                                              3
#define            PCC_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_NUMB                                                             1
#define            PCC_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_RES_VAL                                                          UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_PERIPH_NREQ_POS                                                               2
#define            PCC_ULPD_STATUS_REQ_REG_PERIPH_NREQ_NUMB                                                              1
#define            PCC_ULPD_STATUS_REQ_REG_PERIPH_NREQ_RES_VAL                                                           UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_POS                                                               1
#define            PCC_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_NUMB                                                              1
#define            PCC_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_RES_VAL                                                           UNKNOWN
//R

#define            PCC_ULPD_STATUS_REQ_REG_CHIP_IDLE_POS                                                                 0
#define            PCC_ULPD_STATUS_REQ_REG_CHIP_IDLE_NUMB                                                                1
#define            PCC_ULPD_STATUS_REQ_REG_CHIP_IDLE_RES_VAL                                                             UNKNOWN
//R


//PCC_ULPD_PLL_DIV_REG
//-------------------
#define            PCC_ULPD_PLL_DIV_REG                                                                                REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_PLL_DIV_REG_OFFSET)


#define            PCC_ULPD_PLL_DIV_REG_PLL_DIV_FACTOR_POS                                                               0
#define            PCC_ULPD_PLL_DIV_REG_PLL_DIV_FACTOR_NUMB                                                              16
#define            PCC_ULPD_PLL_DIV_REG_PLL_DIV_FACTOR_RES_VAL                                                           0x0
//R/W


//PCC_ULPD_RESERVED4
//-------------------
#define            PCC_ULPD_RESERVED4                                                                                  REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_RESERVED4_OFFSET)


#define            PCC_ULPD_RESERVED4_RESERVED_POS                                                                       0
#define            PCC_ULPD_RESERVED4_RESERVED_NUMB                                                                      16
#define            PCC_ULPD_RESERVED4_RESERVED_RES_VAL                                                                   0x960
//R


//PCC_ULPD_ULPD_PLL_CTRL_STATUS
//-------------------
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS                                                                       REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_ULPD_PLL_CTRL_STATUS_OFFSET)


#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_POS                                                         15
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_NUMB                                                        1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_RES_VAL                                                     UNKNOWN
//R

#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CTRL_RES_POS                                                        5
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CTRL_RES_NUMB                                                       10
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CTRL_RES_RES_VAL                                                    0x0
//R/W

#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_PWRDNZ_POS                                                              4
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_PWRDNZ_NUMB                                                             1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_PWRDNZ_RES_VAL                                                          0x1
//R/W

#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_TEST_POS                                                                3
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_TEST_NUMB                                                               1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_TEST_RES_VAL                                                            0x0
//R/W

#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL2_POS                                                                2
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL2_NUMB                                                               1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL2_RES_VAL                                                            0x0
//R/W

#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL1_POS                                                                1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL1_NUMB                                                               1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL1_RES_VAL                                                            0x1
//R/W

#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL0_POS                                                                0
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL0_NUMB                                                               1
#define            PCC_ULPD_ULPD_PLL_CTRL_STATUS_SEL0_RES_VAL                                                            0x0
//R/W


//PCC_ULPD_POWER_CTRL_REG
//-------------------
#define            PCC_ULPD_POWER_CTRL_REG                                                                             REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_POWER_CTRL_REG_OFFSET)


#define            PCC_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_POS                                                         12
#define            PCC_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_NUMB                                                        1
#define            PCC_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_RES_VAL                                                     0x0
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_MIN_MAX_REG_POS                                                               11
#define            PCC_ULPD_POWER_CTRL_REG_MIN_MAX_REG_NUMB                                                              1
#define            PCC_ULPD_POWER_CTRL_REG_MIN_MAX_REG_RES_VAL                                                           0x1
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_DVS_ENABLE_POS                                                                10
#define            PCC_ULPD_POWER_CTRL_REG_DVS_ENABLE_NUMB                                                               1
#define            PCC_ULPD_POWER_CTRL_REG_DVS_ENABLE_RES_VAL                                                            0x0
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_OSC_STOP_EN_POS                                                               9
#define            PCC_ULPD_POWER_CTRL_REG_OSC_STOP_EN_NUMB                                                              1
#define            PCC_ULPD_POWER_CTRL_REG_OSC_STOP_EN_RES_VAL                                                           0x1
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_LDO_PWRDOWN_POS                                                               8
#define            PCC_ULPD_POWER_CTRL_REG_LDO_PWRDOWN_NUMB                                                              1
#define            PCC_ULPD_POWER_CTRL_REG_LDO_PWRDOWN_RES_VAL                                                           0x0
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_POS                                                               7
#define            PCC_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_NUMB                                                              1
#define            PCC_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_RES_VAL                                                           0x0
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_LDO_STEADY_POS                                                                6
#define            PCC_ULPD_POWER_CTRL_REG_LDO_STEADY_NUMB                                                               1
#define            PCC_ULPD_POWER_CTRL_REG_LDO_STEADY_RES_VAL                                                            UNKNOWN
//R

#define            PCC_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_POS                                                  4
#define            PCC_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_NUMB                                                 1
#define            PCC_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_RES_VAL                                              0x1
//R/W

#define            PCC_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_POS                                                              3
#define            PCC_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_NUMB                                                             1

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