📄 pcc_ulpd.h
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//PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG
//-------------------
#define PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG_OFFSET)
#define PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG_SETUP_ANALOG_CELL3_POS 0
#define PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG_SETUP_ANALOG_CELL3_NUMB 16
#define PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG_SETUP_ANALOG_CELL3_RES_VAL 0xA0
//R/W
//PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG
//-------------------
#define PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG_OFFSET)
#define PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG_SETUP_ANALOG_CELL2_POS 0
#define PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG_SETUP_ANALOG_CELL2_NUMB 16
#define PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG_SETUP_ANALOG_CELL2_RES_VAL 0x280
//R/W
//PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG
//-------------------
#define PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG_OFFSET)
#define PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG_SETUP_ANALOG_CELL1_POS 0
#define PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG_SETUP_ANALOG_CELL1_NUMB 16
#define PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG_SETUP_ANALOG_CELL1_RES_VAL 0xA0
//R/W
//PCC_ULPD_CLOCK_CTRL_REG
//-------------------
#define PCC_ULPD_CLOCK_CTRL_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_CLOCK_CTRL_REG_OFFSET)
#define PCC_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_POS 6
#define PCC_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_RES_VAL 0x0
//R/W
#define PCC_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_POS 5
#define PCC_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_RES_VAL 0x0
//R/W
#define PCC_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_POS 4
#define PCC_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_RES_VAL 0x0
//R/W
#define PCC_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_POS 3
#define PCC_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_RES_VAL 0x0
//R/W
#define PCC_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_POS 2
#define PCC_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_RES_VAL 0x0
//R/W
#define PCC_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_POS 1
#define PCC_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_RES_VAL 0x0
//R/W
#define PCC_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_POS 0
#define PCC_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_NUMB 1
#define PCC_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_RES_VAL 0x0
//R/W
//PCC_ULPD_SOFT_REQ_REG
//-------------------
#define PCC_ULPD_SOFT_REQ_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_SOFT_REQ_REG_OFFSET)
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_0_REQ_POS 15
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_0_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_0_REQ_RES_VAL 0X0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_EAC12M_DPLL_REQ_POS 14
#define PCC_ULPD_SOFT_REQ_REG_SOFT_EAC12M_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_EAC12M_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_1_REQ_POS 13
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_1_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_1_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_POS 12
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_POS 11
#define PCC_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_2_REQ_POS 10
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_2_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_2_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_POS 9
#define PCC_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_POS 8
#define PCC_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_POS 7
#define PCC_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MCBSP1_REQ_POS 6
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MCBSP1_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MCBSP1_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_NREQ_POS 5
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_NREQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_NREQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_USB_REQ_EN_POS 4
#define PCC_ULPD_SOFT_REQ_REG_USB_REQ_EN_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_USB_REQ_EN_RES_VAL 0x1
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_POS 3
#define PCC_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MCBSP2_REQ_POS 2
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MCBSP2_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_MCBSP2_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_3_REQ_POS 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_3_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_RESERVED_3_REQ_RES_VAL 0x0
//R/W
#define PCC_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_POS 0
#define PCC_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_NUMB 1
#define PCC_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_RES_VAL 0x0
//R/W
//PCC_ULPD_COUNTER_32_FIQ_REG
//-------------------
#define PCC_ULPD_COUNTER_32_FIQ_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_COUNTER_32_FIQ_REG_OFFSET)
#define PCC_ULPD_COUNTER_32_FIQ_REG_COUNTER_32_FIQ_POS 0
#define PCC_ULPD_COUNTER_32_FIQ_REG_COUNTER_32_FIQ_NUMB 8
#define PCC_ULPD_COUNTER_32_FIQ_REG_COUNTER_32_FIQ_RES_VAL 0x01
//R/W
//PCC_ULPD_RESERVED3
//-------------------
#define PCC_ULPD_RESERVED3 REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_RESERVED3_OFFSET)
#define PCC_ULPD_RESERVED3_RESERVED_POS 0
#define PCC_ULPD_RESERVED3_RESERVED_NUMB 16
#define PCC_ULPD_RESERVED3_RESERVED_RES_VAL 0x0
//R
//PCC_ULPD_STATUS_REQ_REG
//-------------------
#define PCC_ULPD_STATUS_REQ_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_STATUS_REQ_REG_OFFSET)
#define PCC_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_POS 15
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