📄 pcc_ulpd.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :perseus2_pcc_ulpd.h
//
// Date of Module Modification:7/1/02
// Date of Generation :7/10/02
//
//
//========================================================================
#ifndef _PCC_ULPD__H
#define _PCC_ULPD__H
#include "global_types.h"
#include "mapping.h"
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define PCC_ULPD_COUNTER_32_LSB_REG_OFFSET 0x000
#define PCC_ULPD_COUNTER_32_MSB_REG_OFFSET 0x004
#define PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG_OFFSET 0x008
#define PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG_OFFSET 0x00C
#define PCC_ULPD_GAUGING_CTRL_REG_OFFSET 0x010
#define PCC_ULPD_IT_STATUS_REG_OFFSET 0x014
#define PCC_ULPD_RESERVED_OFFSET 0x018
#define PCC_ULPD_RESERVED1_OFFSET 0x01C
#define PCC_ULPD_RESERVED2_OFFSET 0x020
#define PCC_ULPD_SETUP_ANALOG_CELL3_ULPD1_REG_OFFSET 0x024
#define PCC_ULPD_SETUP_ANALOG_CELL2_ULPD1_REG_OFFSET 0x028
#define PCC_ULPD_SETUP_ANALOG_CELL1_ULPD1_REG_OFFSET 0x02C
#define PCC_ULPD_CLOCK_CTRL_REG_OFFSET 0x030
#define PCC_ULPD_SOFT_REQ_REG_OFFSET 0x034
#define PCC_ULPD_COUNTER_32_FIQ_REG_OFFSET 0x038
#define PCC_ULPD_RESERVED3_OFFSET 0x03C
#define PCC_ULPD_STATUS_REQ_REG_OFFSET 0x040
#define PCC_ULPD_PLL_DIV_REG_OFFSET 0x044
#define PCC_ULPD_RESERVED4_OFFSET 0x048
#define PCC_ULPD_ULPD_PLL_CTRL_STATUS_OFFSET 0x04C
#define PCC_ULPD_POWER_CTRL_REG_OFFSET 0x050
#define PCC_ULPD_STATUS_REQ_REG2_OFFSET 0x054
#define PCC_ULPD_SLEEP_STATUS_OFFSET 0x058
#define PCC_ULPD_SETUP_ANALOG_CELL4_ULPD1_REG_OFFSET 0x05C
#define PCC_ULPD_SETUP_ANALOG_CELL5_ULPD1_REG_OFFSET 0x060
#define PCC_ULPD_SETUP_ANALOG_CELL6_ULPD1_REG_OFFSET 0x064
#define PCC_ULPD_SOFT_DISABLE_REQ_REG_OFFSET 0x068
#define PCC_ULPD_RESET_STATUS_OFFSET 0x06C
#define PCC_ULPD_REVISION_NUMBER_OFFSET 0x070
#define PCC_ULPD_SDW_CLK_DIV_CTRL_SEL_OFFSET 0x074
#define PCC_ULPD_COM_CLK_DIV_CTRL_SEL_OFFSET 0x078
#define PCC_ULPD_CAM_CLK_CTRL_OFFSET 0x07C
#define PCC_ULPD_SOFT_REQ_REG2_OFFSET 0x080
#define PCC_ULPD_PCC_CTRL_REG_OFFSET 0x100
#define PCC_ULPD_PCC_POWER_CTRL_REG_OFFSET 0x104
#define PCC_ULPD_PCC_PERIPH_CLOCK_SOURCE_SEL_OFFSET 0x108
#define PCC_ULPD_PCC_APLL_LOCK_REGISTER_OFFSET 0x10C
#define PCC_ULPD_PCC_DBB_STATUS_OFFSET 0x120
#define PCC_ULPD_PCC_IT_STATUS_OFFSET 0x124
#define PCC_ULPD_PCC_MASK_IT_OFFSET 0x128
//PCC_ULPD_COUNTER_32_LSB_REG
//-------------------
#define PCC_ULPD_COUNTER_32_LSB_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_COUNTER_32_LSB_REG_OFFSET)
#define PCC_ULPD_COUNTER_32_LSB_REG_COUNTER_SLEEP_CLK_LSB_POS 0
#define PCC_ULPD_COUNTER_32_LSB_REG_COUNTER_SLEEP_CLK_LSB_NUMB 16
#define PCC_ULPD_COUNTER_32_LSB_REG_COUNTER_SLEEP_CLK_LSB_RES_VAL 0x1
//R
//PCC_ULPD_COUNTER_32_MSB_REG
//-------------------
#define PCC_ULPD_COUNTER_32_MSB_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_COUNTER_32_MSB_REG_OFFSET)
#define PCC_ULPD_COUNTER_32_MSB_REG_COUNTER_32_MSB_POS 0
#define PCC_ULPD_COUNTER_32_MSB_REG_COUNTER_32_MSB_NUMB 16
#define PCC_ULPD_COUNTER_32_MSB_REG_COUNTER_32_MSB_RES_VAL 0x0
//R
//PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG
//-------------------
#define PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG_OFFSET)
#define PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG_COUNTER_HIGH_FREQ_LSB_POS 0
#define PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG_COUNTER_HIGH_FREQ_LSB_NUMB 16
#define PCC_ULPD_COUNTER_HIGH_FREQ_LSB_REG_COUNTER_HIGH_FREQ_LSB_RES_VAL 0x1
//R
//PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG
//-------------------
#define PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG_OFFSET)
#define PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG_COUNTER_HIGH_FREQ_MSB_POS 0
#define PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG_COUNTER_HIGH_FREQ_MSB_NUMB 6
#define PCC_ULPD_COUNTER_HIGH_FREQ_MSB_REG_COUNTER_HIGH_FREQ_MSB_RES_VAL 0x0
//R
//PCC_ULPD_GAUGING_CTRL_REG
//-------------------
#define PCC_ULPD_GAUGING_CTRL_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_GAUGING_CTRL_REG_OFFSET)
#define PCC_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_POS 1
#define PCC_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_NUMB 1
#define PCC_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_RES_VAL 0x0
//R/W
#define PCC_ULPD_GAUGING_CTRL_REG_GAUGING_EN_POS 0
#define PCC_ULPD_GAUGING_CTRL_REG_GAUGING_EN_NUMB 1
#define PCC_ULPD_GAUGING_CTRL_REG_GAUGING_EN_RES_VAL 0x0
//R/W
//PCC_ULPD_IT_STATUS_REG
//-------------------
#define PCC_ULPD_IT_STATUS_REG REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_IT_STATUS_REG_OFFSET)
#define PCC_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_POS 3
#define PCC_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_NUMB 1
#define PCC_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_RES_VAL 0x0
//R
#define PCC_ULPD_IT_STATUS_REG_OVERFLOW_32_POS 2
#define PCC_ULPD_IT_STATUS_REG_OVERFLOW_32_NUMB 1
#define PCC_ULPD_IT_STATUS_REG_OVERFLOW_32_RES_VAL 0x0
//R
#define PCC_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_POS 1
#define PCC_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_NUMB 1
#define PCC_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_RES_VAL 0x0
//R
#define PCC_ULPD_IT_STATUS_REG_IT_GAUGING_POS 0
#define PCC_ULPD_IT_STATUS_REG_IT_GAUGING_NUMB 1
#define PCC_ULPD_IT_STATUS_REG_IT_GAUGING_RES_VAL 0x0
//R
//PCC_ULPD_RESERVED
//-------------------
#define PCC_ULPD_RESERVED REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_RESERVED_OFFSET)
#define PCC_ULPD_RESERVED_RESERVED_POS 0
#define PCC_ULPD_RESERVED_RESERVED_NUMB 16
#define PCC_ULPD_RESERVED_RESERVED_RES_VAL 0x3FF
//R
//PCC_ULPD_RESERVED1
//-------------------
#define PCC_ULPD_RESERVED1 REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_RESERVED1_OFFSET)
#define PCC_ULPD_RESERVED1_RESERVED_POS 0
#define PCC_ULPD_RESERVED1_RESERVED_NUMB 16
#define PCC_ULPD_RESERVED1_RESERVED_RES_VAL 0x3FF
//R
//PCC_ULPD_RESERVED2
//-------------------
#define PCC_ULPD_RESERVED2 REG16(PCC_ULPD_BASE_ADDR_ARM+PCC_ULPD_RESERVED2_OFFSET)
#define PCC_ULPD_RESERVED2_RESERVED_POS 0
#define PCC_ULPD_RESERVED2_RESERVED_NUMB 16
#define PCC_ULPD_RESERVED2_RESERVED_RES_VAL 0x3FF
//R
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