📄 nand_flash.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename : nand_flash.h
//
// Date of Module Modification:6/13/02
// Date of Generation :6/25/02
//
// Author: Sebastien Sabatier
//
//========================================================================
#include "test.h"
#ifndef _NAND_FLASH__H
#define _NAND_FLASH__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define NAND_FLASH_NND_REVISION_OFFSET 0x00
#define NAND_FLASH_NND_ACCESS_OFFSET 0x04
#define NAND_FLASH_NND_ADDR_SRC_OFFSET 0x08
#define NAND_FLASH_NND_RESVD_OFFSET 0x0C
#define NAND_FLASH_NND_CTRL_OFFSET 0x10
#define NAND_FLASH_NND_MASK_OFFSET 0x14
#define NAND_FLASH_NND_STATUS_OFFSET 0x18
#define NAND_FLASH_NND_READY_OFFSET 0x1C
#define NAND_FLASH_NND_COMMAND_OFFSET 0x20
#define NAND_FLASH_NND_COMMAND_SEC_OFFSET 0x24
#define NAND_FLASH_NND_ECC_SELECT_OFFSET 0x28
#define NAND_FLASH_NND_ECC1_OFFSET 0x2C
#define NAND_FLASH_NND_ECC2_OFFSET 0x30
#define NAND_FLASH_NND_ECC3_OFFSET 0x34
#define NAND_FLASH_NND_ECC4_OFFSET 0x38
#define NAND_FLASH_NND_ECC5_OFFSET 0x3C
#define NAND_FLASH_NND_ECC6_OFFSET 0x40
#define NAND_FLASH_NND_ECC7_OFFSET 0x44
#define NAND_FLASH_NND_ECC8_OFFSET 0x48
#define NAND_FLASH_NND_ECC9_OFFSET 0x4C
#define NAND_FLASH_NND_RESET_OFFSET 0x50
#define NAND_FLASH_NND_FIFO_OFFSET 0x54
#define NAND_FLASH_NND_FIFOCTRL_OFFSET 0x58
#define NAND_FLASH_NND_PSC_CLK_OFFSET 0x5C
#define NAND_FLASH_NND_SYSTEST_OFFSET 0x60
#define NAND_FLASH_NND_SYSCFG_OFFSET 0x64
#define NAND_FLASH_NND_SYSSTATUS_OFFSET 0x68
#define NAND_FLASH_NND_FIFOTEST1_OFFSET 0x6C
#define NAND_FLASH_NND_FIFOTEST2_OFFSET 0x70
#define NAND_FLASH_NND_FIFOTEST3_OFFSET 0x74
#define NAND_FLASH_NND_FIFOTEST4_OFFSET 0x78
//NAND_FLASH_NND_REVISION
//-------------------
#define NAND_FLASH_NND_REVISION REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_REVISION_OFFSET)
#define NAND_FLASH_NND_REVISION_RESERVED_POS 8
#define NAND_FLASH_NND_REVISION_RESERVED_NUMB 24
#define NAND_FLASH_NND_REVISION_RESERVED_RES_VAL 0x0
//R
#define NAND_FLASH_NND_REVISION_NND_REVISION_POS 0
#define NAND_FLASH_NND_REVISION_NND_REVISION_NUMB 8
#define NAND_FLASH_NND_REVISION_NND_REVISION_RES_VAL 0x00
//R
//NAND_FLASH_NND_ACCESS
//-------------------
#define NAND_FLASH_NND_ACCESS REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_ACCESS_OFFSET)
#define NAND_FLASH_NND_ACCESS_NND_ACCESS_POS 0
#define NAND_FLASH_NND_ACCESS_NND_ACCESS_NUMB 32
#define NAND_FLASH_NND_ACCESS_NND_ACCESS_RES_VAL 0x0000
//R/W
//NAND_FLASH_NND_ADDR_SRC
//-------------------
#define NAND_FLASH_NND_ADDR_SRC REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_ADDR_SRC_OFFSET)
#define NAND_FLASH_NND_ADDR_SRC_NND_ADDR_SRC_POS 0
#define NAND_FLASH_NND_ADDR_SRC_NND_ADDR_SRC_NUMB 32
#define NAND_FLASH_NND_ADDR_SRC_NND_ADDR_SRC_RES_VAL 0x0000
//R/W
//NAND_FLASH_NND_RESVD
//-------------------
#define NAND_FLASH_NND_RESVD REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_RESVD_OFFSET)
//NAND_FLASH_NND_CTRL
//-------------------
#define NAND_FLASH_NND_CTRL REG32(NAND_FLASH_BASE_ADDR_ARM+NAND_FLASH_NND_CTRL_OFFSET)
#define NAND_FLASH_NND_CTRL_RESERVED_0_POS 18
#define NAND_FLASH_NND_CTRL_RESERVED_0_NUMB 14
#define NAND_FLASH_NND_CTRL_RESERVED_0_RES_VAL 0x0
//R
#define NAND_FLASH_NND_CTRL_PREFETCH_POS 17
#define NAND_FLASH_NND_CTRL_PREFETCH_NUMB 1
#define NAND_FLASH_NND_CTRL_PREFETCH_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_POSTWRITE_POS 16
#define NAND_FLASH_NND_CTRL_POSTWRITE_NUMB 1
#define NAND_FLASH_NND_CTRL_POSTWRITE_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT3_POS 15
#define NAND_FLASH_NND_CTRL_WRITEPROT3_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT3_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN3_POS 14
#define NAND_FLASH_NND_CTRL_CHIPEN3_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN3_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT2_POS 13
#define NAND_FLASH_NND_CTRL_WRITEPROT2_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT2_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN2_POS 12
#define NAND_FLASH_NND_CTRL_CHIPEN2_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN2_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT1_POS 11
#define NAND_FLASH_NND_CTRL_WRITEPROT1_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT1_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN1_POS 10
#define NAND_FLASH_NND_CTRL_CHIPEN1_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN1_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_WRITEPROT0_POS 9
#define NAND_FLASH_NND_CTRL_WRITEPROT0_NUMB 1
#define NAND_FLASH_NND_CTRL_WRITEPROT0_RES_VAL 0x0
//R/W
#define NAND_FLASH_NND_CTRL_CHIPEN0_POS 8
#define NAND_FLASH_NND_CTRL_CHIPEN0_NUMB 1
#define NAND_FLASH_NND_CTRL_CHIPEN0_RES_VAL 0x1
//R/W
#define NAND_FLASH_NND_CTRL_RESERVED_1_POS 7
#define NAND_FLASH_NND_CTRL_RESERVED_1_NUMB 1
#define NAND_FLASH_NND_CTRL_RESERVED_1_RES_VAL 0x0
//R
#define NAND_FLASH_NND_CTRL_ADDRCNT_POS 5
#define NAND_FLASH_NND_CTRL_ADDRCNT_NUMB 2
#define NAND_FLASH_NND_CTRL_ADDRCNT_RES_VAL 0x00
//R/W
#define NAND_FLASH_NND_CTRL_A8_POS 4
#define NAND_FLASH_NND_CTRL_A8_NUMB 1
#define NAND_FLASH_NND_CTRL_A8_RES_VAL 0x0
//R/W
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