📄 inth2.h
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//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Filename : inth2.h
//===============================================================================
#ifndef _INTH2__HH
#define _INTH2__HH
#include "inth.h"
#include "errorcodes.h"
#define FALLING_EDGE_SENSITIVE INTH_FALLING_EDGE_SENSITIVE
#define LOW_LEVEL_SENSITIVE INTH_LOW_LEVEL_SENSITIVE
#define INTH_MASK_IT 1
#define INTH_UNMASK_IT 0
#define IT_DETECTED 1
#define IT_NOT_DETECTED 0
//##################################################################
// OFFSET OF THE 32 bits REGISTERS
//##################################################################
// Internal interrupt handler
//============================
#define LEV1_INTH_IT_REG_OFFSET INTH_IT_REG_OFFSET // Interrupt register offset
#define LEV1_INTH_MASK_IT_REG_OFFSET INTH_MASK_IT_REG_OFFSET // Mask Interrupt register offset
#define LEV1_INTH_SOURCE_IRQ_REG_OFFSET INTH_SOURCE_IRQ_REG_OFFSET // Active IRQ
#define LEV1_INTH_SOURCE_FIQ_REG_OFFSET INTH_SOURCE_FIQ_REG_OFFSET // Active FIQ
#define LEV1_INTH_SOURCE_BIN_IRQ_REG_OFFSET INTH_SOURCE_BIN_IRQ_REG_OFFSET // Srce Binary coded IRQ register offset
#define LEV1_INTH_SOURCE_BIN_FIQ_REG_OFFSET INTH_SOURCE_BIN_FIQ_REG_OFFSET // Srce Binary coded FIQ register offset
#define LEV1_INTH_CTRL_REG_OFFSET INTH_CTRL_REG_OFFSET // Control register offset
#define LEV1_INTH_IT_LEVEL_REG_OFFSET INTH_IT_LEVEL_REG_OFFSET // Interrupt Level registers offset
// EXternal interrupt handler
//============================
#define LEV2_INTH_IT_REG_OFFSET INTH_IT_REG_OFFSET // Interrupt register offset
#define LEV2_INTH_MASK_IT_REG_OFFSET INTH_MASK_IT_REG_OFFSET // Mask Interrupt register offset
#define LEV2_INTH_SOURCE_IRQ_REG_OFFSET INTH_SOURCE_IRQ_REG_OFFSET // Active IRQ
#define LEV2_INTH_SOURCE_FIQ_REG_OFFSET INTH_SOURCE_FIQ_REG_OFFSET // Active FIQ
#define LEV2_INTH_SOURCE_BIN_IRQ_REG_OFFSET INTH_SOURCE_BIN_IRQ_REG_OFFSET // Srce Binary coded IRQ register offset
#define LEV2_INTH_SOURCE_BIN_FIQ_REG_OFFSET INTH_SOURCE_BIN_FIQ_REG_OFFSET // Srce Binary coded FIQ register offset
#define LEV2_INTH_CTRL_REG_OFFSET INTH_CTRL_REG_OFFSET // Control register offset
#define LEV2_INTH_IT_LEVEL_REG_OFFSET INTH_IT_LEVEL_REG_OFFSET // Interrupt Level registers offset
//######################################
// IT_REGISTER Internal and External
// Contains the pending requests
// READ ONLY and RESET and Clear
//########################################
// Internal interrupt handler
//============================
//
#define LEV1_INTH_IT_REG_USER_ADDR INTH_IT_REG_USER_ADDR
#define LEV1_INTH_IT_REG_SUPERVISOR_ADDR INTH_IT_REG_SUPERVISOR_ADDR
#define LEV1_INTH_IT_REG_RESET_VALUE INTH_IT_REG_RESET_VALUE
//
#define LEV1_INTH_IT_REG LEV1_INTH_IT_REG_USER_ADDR
#define LEV1_INTH_IT_REG_RES_VAL INTH_IT_REG_RESET_VALUE
// External interrupt handler
//============================
#define LEV2_INTH_IT_REG_USER_ADDR ( ARMINTH_L20_BASE_ADDR_ARM + INTH_IT_REG_OFFSET )
#define LEV2_INTH_IT_REG_SUPERVISOR_ADDR ( ARMINTH_L20_BASE_ADDR_ARM + INTH_IT_REG_OFFSET )
#define LEV2_INTH_IT_REG_RESET_VALUE INTH_IT_REG_RESET_VALUE
#define LEV2_INTH_IT_REG LEV2_INTH_IT_REG_USER_ADDR
#define LEV2_INTH_IT_REG_RES_VAL INTH_IT_REG_RESET_VALUE
//########################################
// MASK_INTERRUPT_REGISTER (read/Write)
// Contains the pending requests
// READ ONLY and RESET and Clear
//##########################################
// Internal interrupt handler
//============================
//
#define LEV1_INTH_MASK_IT_REG_USER_ADDR INTH_MASK_IT_REG_USER_ADDR
#define LEV1_INTH_MASK_IT_REG_SUPERVISOR_ADDR INTH_MASK_IT_REG_SUPERVISOR_ADDR
#define LEV1_INTH_MASK_IT_REG_RESET_VALUE INTH_MASK_IT_REG_RESET_VALUE
// External interrupt handler
//============================
#define LEV2_INTH_MASK_IT_REG_USER_ADDR ( LEV2_INTH_IT_REG_USER_ADDR + INTH_MASK_IT_REG_OFFSET )
#define LEV2_INTH_MASK_IT_REG_SUPERVISOR_ADDR ( LEV2_INTH_IT_REG_SUPERVISOR_ADDR + INTH_MASK_IT_REG_OFFSET )
#define LEV2_INTH_MASK_IT_REG_RESET_VALUE INTH_MASK_IT_REG_RESET_VALUE
#define LEV2_INTH_MASK_IT_REG LEV2_INTH_MASK_IT_REG_USER_ADDR
#define LEV2_INTH_MASK_IT_REG_RES_VAL INTH_MASK_IT_REG_RESET_VALUE
//##################################################################
// INTERRUPT LEVEL REGISTERS (READ/WRITE)
// define all the interrupt and their respective attributes
// - Kind of IT : either IFQ or IRQ
// - Priority : Priority level to process the request
// - Sensitive Edge: Either Falling Edge or Low Level Sensitive
//##################################################################
// Internal interrupt handler
//============================
//
#define LEV1_INTH_IT_LEVEL_REG_SUPERVISOR_ADDR INTH_IT_LEVEL_REG_SUPERVISOR_ADDR
#define LEV1_INTH_IT_LEVEL_REG_USER_ADDR INTH_IT_LEVEL_REG_USER_ADDR
#define LEV1_INTH_IT_LEVEL_MASK INTH_IT_LEVEL_MASK
#define LEV1_INTH_IT_LEVEL_RESET_VALUE INTH_IT_LEVEL_RESET_VALUE
//
// External interrupt handler
//============================
#define LEV2_INTH_IT_LEVEL_REG_SUPERVISOR_ADDR ( LEV2_INTH_IT_REG_SUPERVISOR_ADDR + LEV2_INTH_IT_LEVEL_REG_OFFSET )
#define LEV2_INTH_IT_LEVEL_REG_USER_ADDR ( LEV2_INTH_IT_REG_USER_ADDR + LEV2_INTH_IT_LEVEL_REG_OFFSET )
#define LEV2_INTH_IT_LEVEL_MASK INTH_IT_LEVEL_MASK
#define LEV2_INTH_IT_LEVEL_RESET_VALUE INTH_IT_LEVEL_RESET_VALUE
#define LEV2_INTH_LEVEL_FIQ_POS 0
#define LEV2_INTH_LEVEL_FIQ_NUMB 1
#define LEV2_INTH_LEVEL_FIQ_RES_VAL 0
#define LEV2_INTH_LEVEL_SENSEDGE_POS 1
#define LEV2_INTH_LEVEL_SENSEDGE_NUMB 1
#define LEV2_INTH_LEVEL_SENSEDGE_RES_VAL 0
#define LEV2_INTH_LEVEL_PRIORITY_POS 2
#define LEV2_INTH_LEVEL_PRIORITY_NUMB 5
#define LEV2_INTH_LEVEL_PRIORITY_RES_VAL 0
//########################################
// Source IRQ Register (read)
// Source FIQ Register (read)
// These two registers are only used for
// the test of reset values !
//##########################################
// External interrupt handler
//============================
#define LEV2_INTH_SOURCE_IRQ_REG ( LEV2_INTH_IT_REG_USER_ADDR + LEV2_INTH_SOURCE_IRQ_REG_OFFSET )
#define LEV2_INTH_SOURCE_IRQ_REG_RES_VAL 0x0000
#define LEV2_INTH_SOURCE_FIQ_REG ( LEV2_INTH_IT_REG_USER_ADDR + LEV2_INTH_SOURCE_FIQ_REG_OFFSET )
#define LEV2_INTH_SOURCE_FIQ_REG_RES_VAL 0x0000
//###############################################
// SOURCE_IRQ (Binary coded)
// The register indicates the interrupt number
// having requested a MCU action
//#################################################
// Internal interrupt handler
//============================
#define LEV1_INTH_SOURCE_BIN_IRQ_REG_ADDR INTH_SOURCE_BIN_IRQ_REG_ADDR
#define LEV1_INTH_SOURCE_BIN_IRQ_RESET_VALUE INTH_SOURCE_BIN_IRQ_RESET_VALUE
#define LEV1_INTH_SOURCE_BIN_IRQ_MASK INTH_SOURCE_BIN_IRQ_MASK
//
// External interrupt handler
//============================
#define LEV2_INTH_SOURCE_BIN_IRQ_REG_ADDR ( LEV2_INTH_IT_REG_USER_ADDR + LEV2_INTH_SOURCE_BIN_IRQ_REG_OFFSET )
#define LEV2_INTH_SOURCE_BIN_IRQ_RESET_VALUE INTH_SOURCE_BIN_IRQ_RESET_VALUE
#define LEV2_INTH_SOURCE_BIN_IRQ_MASK INTH_SOURCE_BIN_IRQ_MASK
#define LEV2_INTH_SOURCE_BIN_IRQNUM_POS 0
#define LEV2_INTH_SOURCE_BIN_IRQNUM_NUMB 5
#define LEV2_INTH_SOURCE_BIN_IRQNUM_RES_VAL 0
//###############################################
// SOURCE_FIQ (Binary coded)
// The register indicates the interrupt number
// having requested a MCU action
//#################################################
// Internal interrupt handler
//============================
#define LEV1_INTH_SOURCE_BIN_FIQ_REG_ADDR INTH_SOURCE_BIN_FIQ_REG_ADDR
#define LEV1_INTH_SOURCE_BIN_FIQ_RESET_VALUE INTH_SOURCE_BIN_FIQ_RESET_VALUE
#define LEV1_INTH_SOURCE_BIN_FIQ_MASK INTH_SOURCE_BIN_FIQ_MASK
//
// External interrupt handler
//============================
#define LEV2_INTH_SOURCE_BIN_FIQ_REG_ADDR ( LEV2_INTH_IT_REG_USER_ADDR + LEV2_INTH_SOURCE_BIN_FIQ_REG_OFFSET )
#define LEV2_INTH_SOURCE_BIN_FIQ_RESET_VALUE INTH_SOURCE_BIN_FIQ_RESET_VALUE
#define LEV2_INTH_SOURCE_BIN_FIQ_MASK INTH_SOURCE_BIN_FIQ_MASK
#define LEV2_INTH_SOURCE_BIN_FIQNUM_POS 0
#define LEV2_INTH_SOURCE_BIN_FIQNUM_NUMB 5
#define LEV2_INTH_SOURCE_BIN_FIQNUM_RES_VAL 0
//##################################################################
// CONTROL REGISTER
// READ/WRITE
//##################################################################
// Internal interrupt handler
//============================
#define LEV1_INTH_CTRL_REG_USER_ADDR INTH_CTRL_REG_USER_ADDR
#define LEV1_INTH_CTRL_REG_SUPERVISOR_ADDR INTH_CTRL_REG_SUPERVISOR_ADDR
#define LEV1_INTH_CTRL_MASK INTH_CTRL_MASK
#define LEV1_INTH_CTRL_RESET_VALUE INTH_CTRL_RESET_VALUE
// External interrupt handler
//============================
#define LEV2_INTH_CTRL_REG_USER_ADDR ( LEV2_INTH_IT_REG_USER_ADDR + LEV2_INTH_CTRL_REG_OFFSET )
#define LEV2_INTH_CTRL_REG_SUPERVISOR_ADDR ( LEV2_INTH_IT_REG_SUPERVISOR_ADDR + LEV2_INTH_CTRL_REG_OFFSET )
#define LEV2_INTH_CTRL_MASK INTH_CTRL_MASK
#define LEV2_INTH_CTRL_RESET_VALUE INTH_CTRL_RESET_VALUE
#define LEV2_INTH_CTRL_NEWIRQAGR_POS 0
#define LEV2_INTH_CTRL_NEWIRQAGR_NUMB 1
#define LEV2_INTH_CTRL_NEWIRQAGR_RES_VAL 0
#define LEV2_INTH_CTRL_NEWFIQAGR_POS 1
#define LEV2_INTH_CTRL_NEWFIQAGR_NUMB 1
#define LEV2_INTH_CTRL_NEWFIQAGR_RES_VAL 0
//###########################################################################################
// Bit definition of Interrupt Level Registers (Same for external and internal)
//###########################################################################################
// Internal interrupt handler
//============================
#define LEV1_INTH_FIQNIRQ_POSBIT INTH_FIQNIRQ_POSBIT
#define LEV1_INTH_PRIORITY_POSBIT INTH_PRIORITY_POSBIT
#define LEV1_INTH_SENSITIVE_EDGE_POSBIT INTH_SENSITIVE_EDGE_POSBIT
#define LEV1_INTH_FIQ_MASK INTH_FIQ_MASK
#define LEV1_INTH_PRIORITY_MASK INTH_PRIORITY_MASK
#define LEV1_INTH_SENSITIVE_EDGE_MASK INTH_SENSITIVE_EDGE_MASK
// External interrupt handler
//============================
#define LEV2_INTH_FIQNIRQ_POSBIT INTH_FIQNIRQ_POSBIT
#define LEV2_INTH_PRIORITY_POSBIT INTH_PRIORITY_POSBIT
#define LEV2_INTH_SENSITIVE_EDGE_POSBIT INTH_SENSITIVE_EDGE_POSBIT
#define LEV2_INTH_FIQ_MASK INTH_FIQ_MASK
#define LEV2_INTH_PRIORITY_MASK INTH_PRIORITY_MASK
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