mcbsp.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//--------------------------------------
//-- MCBSP_PIN_OUT_AS_MASTER (PCR param)
//--------------------------------------
//--  FSX  out
//--  FSR   out
//--  CLKX  out
//--   CLKR  out
//--  data clocked on rising edge of SCK (CLKX)
//--  data sampled on falling edge of SCK (CLKX)
#define  MCBSP_PIN_OUT_AS_MASTER                 REG16(MCBSP_PCR_REG) = 0x0F00

//--------------------------------------
//-- MCBSP_PIN_OUT_AS_SLAVE (PCR param)
//--------------------------------------
//--  FSX  input 
//--  FSR   input
//--  CLKX  input
//--   CLKR  input
//--  data clocked on rising edge of SCK (CLKX)
//--  data sampled on falling edge of SCK (CLKX)
//------------------------------
#define  MCBSP_PIN_OUT_AS_SLAVE                  REG16(MCBSP_PCR_REG) = 0x0000

//-----------------------------------------
//-- MCBSP_RECEIVER_16_BITS_I2S (RCR param)
//-----------------------------------------
//--  dual phase receive
//--  16 bits receive word length (phase 1)
//--  16 bits receive word length (phase 2)
//--  1 word receive frame length (phase 1)
//--  1 word receive frame length (phase 2)
//--  no companding, receive with MSB first
//--  received frame-synchro pulses after the first are ignored
//--  1 bit data delay
#define MCBSP_RECEIVER_16_BITS_I2S              REG16(MCBSP_RCR1_REG) = 0x0040;\
                                               REG16(MCBSP_RCR2_REG) = 0x8045

//--------------------------------------------
//-- MCBSP_TRANSMITTER_16_BITS_I2S (XCR param)
//--------------------------------------------
//--  dual phase transmit
//--  16 bits transmit word length (phase 1)
//--  16 bits transmit word length (phase 2)
//--  1 word transmit frame length (phase 1)
//--  1 word transmit frame length (phase 2)
//--  no companding, transfert with MSB first
//--  transmitted frame-synchro pulses after the first are not ignored
//--  1 bit data delay
#define MCBSP_TRANSMITTER_16_BITS_I2S           REG16(MCBSP_XCR1_REG) = 0x0040;\
                                                REG16(MCBSP_XCR2_REG) = 0x8041

//----------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_I2S_MODULE_CLOCK_DRIVE (SRGR param)
//----------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  32 Cycle Frame Period (31+1)
//--  16 Cycle Frame active duration (15+1)
//--  CLKX= module clock divided by 2 (1+1)

#define MCBSP_SRGR_16_BITS_MASTER_I2S_MODULE_CLOCK_DRIVE REG16(MCBSP_SRGR1_REG) = 0x0f01;\
                                                         REG16(MCBSP_SRGR2_REG) = 0x301f
//----------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_I2S_MODULE_CLOCK_DRIVE_DIV8 (SRGR param)
//----------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  32 Cycle Frame Period (31+1)
//--  16 Cycle Frame active duration (15+1)
//--  CLKX= module clock divided by 8 (7+1)

#define MCBSP_SRGR_16_BITS_MASTER_I2S_MODULE_CLOCK_DRIVE_DIV8 REG16(MCBSP_SRGR1_REG) = 0x0f07;\
                                                              REG16(MCBSP_SRGR2_REG) = 0x301f

//---------------------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_I2S_CLKS_CLOCK_DRIVE_48K_SAMPLING (SRGR param)
//---------------------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  32 Cycle Frame Period (31+1)
//--  16 Cycle Frame active duration (15+1)
//--  CLKX= external CLKS clock divided by 8 (7+1)
#define MCBSP_SRGR_16_BITS_MASTER_I2S_CLKS_CLOCK_DRIVE_48K_SAMPLING REG16(MCBSP_SRGR1_REG) = 0x0f07;\
                                                       REG16(MCBSP_SRGR2_REG) = 0x101f

//-------------------------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_I2S_CLKS_CLOCK_DRIVE_44_1K_SAMPLING (SRGR param)
//-------------------------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  32 Cycle Frame Period (31+1)
//--  16 Cycle Frame active duration (15+1)
//--  CLKX= external CLKS clock divided by 8 (7+1)
#define MCBSP_SRGR_16_BITS_MASTER_I2S_CLKS_CLOCK_DRIVE_44_1K_SAMPLING REG16(MCBSP_SRGR1_REG) = 0x0f07;\
                                                       REG16(MCBSP_SRGR2_REG) = 0x101f

//---------------------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_I2S_CLKS_CLOCK_DRIVE_32K_SAMPLING (SRGR param)
//---------------------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  32 Cycle Frame Period (31+1)
//--  16 Cycle Frame active duration (15+1)
//--  CLKX= external CLKS clock divided by 12 (11+1)
#define MCBSP_SRGR_16_BITS_MASTER_I2S_CLKS_CLOCK_DRIVE_32K_SAMPLING REG16(MCBSP_SRGR1_REG) = 0x0f0b;\
                                                       REG16(MCBSP_SRGR2_REG) = 0x101f


//------------------------------------------------------------------------------------------------------
//                                 PCM specific part                                                    
//------------------------------------------------------------------------------------------------------

//-----------------------------------------
//-- MCBSP_RECEIVER_16_BITS_PCM (RCR param)
//-----------------------------------------
//--  dual phase receive
//--  32 bits receive word length (phase 1)
//--  32 bits receive word length (phase 2)
//--  1 word receive frame length (phase 1)
//--  1 word receive frame length (phase 2)
//--  no companding, receive with MSB first
//--  received frame-synchro pulses after the first are ignored
//--  0 bit data delay
#define MCBSP_RECEIVER_16_BITS_PCM             REG16(MCBSP_RCR1_REG) = 0x00A0;\
                                               REG16(MCBSP_RCR2_REG) = 0x80A4

//--------------------------------------------
//-- MCBSP_TRANSMITTER_16_BITS_PCM (XCR param)
//--------------------------------------------
//--  dual phase transmit
//--  32 bits transmit word length (phase 1)
//--  32 bits transmit word length (phase 2)
//--  1 word transmit frame length (phase 1)
//--  1 word transmit frame length (phase 2)
//--  no companding, transfert with MSB first
//--  transmitted frame-synchro pulses after the first are not ignored
//--  0 bit data delay
#define MCBSP_TRANSMITTER_16_BITS_PCM           REG16(MCBSP_XCR1_REG) = 0x00A0;\
                                                REG16(MCBSP_XCR2_REG) = 0x80A0

//---------------------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_PCM_CLKS_CLOCK_DRIVE_48K_SAMPLING (SRGR param)
//---------------------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  64 Cycle Frame Period (63+1)
//--  32 Cycle Frame active duration (31+1)
//--  CLKX= external CLKS clock divided by 4 (3+1)
#define MCBSP_SRGR_16_BITS_MASTER_PCM_CLKS_CLOCK_DRIVE_48K_SAMPLING REG16(MCBSP_SRGR1_REG) = 0x1f03;\
                                                       REG16(MCBSP_SRGR2_REG) = 0x103f

//---------------------------------------------------------------------------
//-- MCBSP_SRGR_16_BITS_MASTER_PCM_CLKS_CLOCK_DRIVE_32K_SAMPLING (SRGR param)
//---------------------------------------------------------------------------
//--  frame synchro generated by simple rate generator
//--  64 Cycle Frame Period (63+1)
//--  32 Cycle Frame active duration (31+1)
//--  CLKX= external CLKS clock divided by 6 (5+1)
#define MCBSP_SRGR_16_BITS_MASTER_PCM_CLKS_CLOCK_DRIVE_32K_SAMPLING REG16(MCBSP_SRGR1_REG) = 0x1f05;\
                                                       REG16(MCBSP_SRGR2_REG) = 0x103f
//------------------------------------------
//-- MCBSP_PIN_OUT_AS_MASTER PCM (PCR param)
//------------------------------------------
//--  FSX  out
//--  FSR   out
//--  CLKX  out
//--   CLKR  out
//--  data clocked on rising edge of SCK (CLKX)
//--  data sampled on falling edge of SCK (CLKX)
//--     receive frame synchro active low
//--     transmit frame synchro active low
#define  MCBSP_PIN_OUT_AS_MASTER_PCM             REG16(MCBSP_PCR_REG) = 0x0F0C


void MCBSP_TestResetValue(void);

// Mask definition
//----------------

#define XRST_MASK 1
#define RRST_MASK 1

// types definition
//-----------------

typedef enum { MCBSP_CLKSTP_without_delay = 2,
               MCBSP_CLKSTP_with_delay = 3
               } MCBSP_CLKSTP_t;

typedef enum { MCBSP_RXClockFallingEdge = 0,
               MCBSP_RXClockRisingEdge = 1,
               MCBSP_TXClockRisingEdge = 0,
               MCBSP_TXClockFallingEdge = 1
             } MCBSP_ClkPol_t;

typedef enum { MCBSP_FSActiveHigh = 0,
               MCBSP_FSActiveLow = 1
             } MCBSP_FSActive_t;

typedef enum { MCBSP_ClockInput = 0,
               MCBSP_ClockOutput = 1
             } MCBSP_ClockMode_t;

typedef enum { MCBSP_FSExternal = 0,
               MCBSP_FSInternal = 1
             } MCBSP_FSSync_t;

typedef enum { MCBSP_GPIODisable = 0,
               MCBSP_GPIOEnable = 1
             } MCBSP_GPIOInput_t;

typedef enum { MCBSP_WordLength_8Bits = 0,
               MCBSP_WordLength_12Bits = 1,
               MCBSP_WordLength_16Bits = 2,
               MCBSP_WordLength_20Bits = 3,
               MCBSP_WordLength_24Bits = 4,
               MCBSP_WordLength_32Bits = 5
             } MCBSP_WordLength_t;

typedef enum { MCBSP_FrameLength_1Words = 0,
               MCBSP_FrameLength_2Words = 1
             } MCBSP_FrameLength_t;

typedef enum { MCBSP_DataDelay_0Bits = 0,
               MCBSP_DataDelay_1Bits = 1,
               MCBSP_DataDelay_2Bits = 2
             } MCBSP_DataDelay_t;

typedef enum { MCBSP_FrameNotIgnore = 0,
               MCBSP_FrameIgnore = 1
             } MCBSP_FrameIgnore_t;

typedef enum { MCBSP_NoCompanding_MSBFirst = 0,
               MCBSP_NoCompanding_LSBFirst = 1,
               MCBSP_Companding_uLaw = 2,
               MCBSP_Companding_ALaw = 3
             } MCBSP_Companding_t;

typedef enum { MCBSP_SinglePhase = 0,
               MCBSP_DualPhase = 1
             } MCBSP_Phase_t;

typedef enum { MCBSP_ClockDividedBy_1 = 0,
               MCBSP_ClockDividedBy_2 = 1,
               MCBSP_ClockDividedBy_4 = 3,
               MCBSP_ClockDividedBy_6 = 5,
               MCBSP_ClockDividedBy_12 = 11,
               MCBSP_ClockDividedBy_24 = 23,
               MCBSP_ClockDividedBy_48 = 47,
               MCBSP_ClockDividedBy_120 = 119
             } MCBSP_ClockDivider_t;

typedef enum { MCBSP_FrameWidth_1 = 0,
               MCBSP_FrameWidth_2 = 1,
               MCBSP_FrameWidth_16 = 15
             } MCBSP_FrameWidth_t;

typedef enum { MCBSP_FramePeriod_1 = 0,
               MCBSP_FramePeriod_2 = 1,
               MCBSP_FramePeriod_9 = 8,
               MCBSP_FramePeriod_17 = 16,
               MCBSP_FramePeriod_32 = 31,
               MCBSP_FramePeriod_64 = 63,
               MCBSP_FramePeriod_128 = 127,
               MCBSP_FramePeriod_256 = 255,
               MCBSP_FramePeriod_512 = 511,
               MCBSP_FramePeriod_800 = 799,
               MCBSP_FramePeriod_1024 = 1023,
               MCBSP_FramePeriod_2500 = 2499
             } MCBSP_FramePeriod_t;

typedef enum { MCBSP_FSCopy = 0,
               MCBSP_FSDriven = 1
             } MCBSP_FSMode_t;

typedef enum { MCBSP_SampleExternal = 0,
               MCBSP_SampleInternal = 1
             } MCBSP_SampleMode_t;

typedef enum { MCBSP_CLKSFallingEdge = 0,
               MCBSP_CLKSRisingEdge = 1
             } MCBSP_CLKSPol_t;

typedef enum { MCBSP_FreeRunning = 0,
               MCBSP_ReSynchronize = 1
             } MCBSP_SampleSync_t;

typedef enum { MCBSP_Disable = 0,
               MCBSP_Enable = 1
             } MCBSP_Enable_t;

typedef enum { MCBSP_DRR1 = 0,
               MCBSP_DRR2 = 1,
               MCBSP_DXR1 = 2,
               MCBSP_DXR2 = 3
             } MCBSP_DataRegister_t;



#endif