mcbsp.h

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#define XWDLEN1_SZ  3 /* size in bit */
/* XWDLEN1 = 000 8 bits 
XWDLEN1 = 001 12 bits 
XWDLEN1 = 010 16 bits 
XWDLEN1 = 011 20 bits 
XWDLEN1 = 100 24 bits 
XWDLEN1 = 101 32 bits 
XWDLEN1 = 11X Reserved */

/**************
MCBSP_SRGR2_REG  
***************/
#define GSYNC    15 /* Sample Rate Generator Clock Synchronization,used when the external clock drives the sample rate generator */
#define GSYNC_SZ  1 /* size in bit */
/* GSYNC = 0 The sample rate generator clock (CLKG) is free running. 
GSYNC = 1 The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame-sync signal (FSG) is generated 
only after detecting the receive frame-synchronization signal (FSR). */ 


#define CLKSP    14 /* CLKS Polarity Clock Edge Select used when the external clock drives the sample rate generator clock */
#define CLKSP_SZ  1 /* size in bit */
/* CLKSP = 0 Rising edge of CLKS generates CLKG and FSG. 
  CLKSP = 1 Falling edge of CLKS generates CLKG and FSG. */
 
#define CLKSM    13 /* McBSP Sample Rate Generator Clock Mode */
#define CLKSM_SZ  1 /* size in bit */
/* CLKSM = 0 Sample rate generator clock derived from the CLKS pin. 
CLKSM = 1 Sample rate generator clock derived from CPU clock.*/

#define FSGM    12 /* Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR. */
#define FSGM_SZ    1  /* size in bit */
/* FSGM = 0 Transmit frame-sync signal (FSX) due to DXR[1,2]-to-XSR[1,2] copy. When FSGM = 0, FPR and FWID are ignored. 
FSGM = 1 Transmit frame-sync signal driven by the sample rate generator frame-sync signal, FSG. */

#define FPER    11 /* Frame Period. */
#define FPER_SZ    12 /* size in bit */
/*This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods*/

/**************
MCBSP_SRGR1_REG
***************/
#define FWID    15 /* Frame Width. */
#define FWID_SZ    8  /* size in bit */
/* This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: up to 2; 1 to 256 CLKG
periods.*/

#define CLKGDV    7 /* Sample Rate Generator Clock Divider */
#define CLKGDV_SZ  8 /* size in bit */
/*This value is used as the divide-down number to generate the required sample rate generator clock frequency. Default value is 1. */


/**************  
MCBSP_PCR_REG  
***************/

#define XIOEN    13 /* Transmit general purpose I/O mode only when XRST = 0 in SPCR[1,2] */
#define XIOEN_SZ  1 /* size in bit */
/*XIOEN = 0 DX, FSX and CLKX are configured as serial port pins and do not function as general-purpose I/Os. 
XIOEN = 1 DX pin is a general purpose output. FSX and CLKX are general purpose I/Os. */

   
#define RIOEN    12 /* Receive general purpose I/O mode only when RRST = 0 in SPCR[1,2] */
#define RIOEN_SZ  1 /* size in bit */
/*RIOEN = 0 DR, FSR, CLKR and CLKS are configured as serial port pins and do not function as general-purpose I/Os. 
RIOEN = 1 DR and CLKS pins are general purpose inputs; FSR and CLKR are general purpose I/Os. */


#define FSXM    11 /* Transmit Frame-Synchronization Mode */
#define FSXM_SZ    1 /* size in bit */
/*FSXM = 0 Frame-synchronization signal derived from an external source 
FSXM = 1 Frame synchronization is determined by the sample rate generator frame-synchronization mode bit FSGM in SRGR2. */

#define FSRM    10 /* Receive Frame-Synchronization Mode */
#define FSRM_SZ    1 /* size in bit */
/*FSRM = 0 Frame-synchronization pulses generated by an external device. FSR is an input pin 
FSRM = 1 Frame synchronization generated internally by sample rate generator. */


#define CLKXM    9 /*Transmitter Clock Mode */
#define CLKXM_SZ  1 /* size in bit */
/*CLKXM = 0 Transmitter clock is driven by an external clock with CLKX as an input pin. 
CLKXM = 1 CLKX is an output pin and is driven by the internal sample rate generator. */
 
#define CLKRM    8  /* Receiver Clock Mode */
#define CLKRM_SZ  1 /* size in bit */
/*Case 1: Digital loop back mode not set (DLB = 0) in SPCR1 
CLKRM = 0 Receive clock (CLKR) is an input driven by an external clock. 
CLKRM = 1 CLKR is an output pin and is driven by the internal sample rate generator. 
Case 2: Digital loop back mode set (DLB=1) in SPCR1 
CLKRM = 0 Receive clock (not the CLKR pin) is driven by transmit clock (CLKX) which is based on the CLKXM bit in the PCR. 
CLKR pin is in high-impedance. 
CLKRM = 1 CLKR is an output pin and is driven by the transmit clock. 
The transmit clock is derived based on the CLKXM bit in the the PCR. */



#define CLKS_STAT  6 /*CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input.*/
#define CLKS_STAT_SZ  1 /* size in bit */

#define DX_STAT    5 /* DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. */
#define DX_STAT_SZ  1 /* size in bit */

#define DR_STAT    4 /* DR pin status. Reflects value on DR pin when selected as a general purpose input. */
#define DR_STAT_SZ  1 /* size in bit */

#define FSXP    3 /* Transmit Frame-Synchronization Polarity */
#define FSXP_SZ    1 /* size in bit */
/*FSXP = 0 Frame-synchronization pulse FSX is active high 
FSXP = 1 Frame-synchronization pulse FSX is active low */

#define FSRP    2 /* Receive Frame-Synchronization Polarity */
#define FSRP_SZ    1 /* size in bit */
/*FSRP = 0 Frame-synchronization pulse FSR is active high 
FSRP = 1 Frame-synchronization pulse FSR is active low */

#define CLKXP    1 /* Transmit Clock Polarity */
#define CLKXP_SZ  1 /* size in bit */
/*CLKXP = 0 Transmit data sampled on rising edge of CLKX 
CLKXP = 1 Transmit data sampled on falling edge of CLKX */

#define CLKRP    0 /* Receive Clock Polarity */
#define CLKRP_SZ  1 /* size in bit */
/*CLKRP = 0 Receive data sampled on falling edge of CLKR 
CLKRP = 1 Receive data sampled on rising edge of CLKR
*/

/**************
MCBSP_MCR2_REG
***************/

#define XMCM              1
#define XMCM_SZ         2  /* size in bit */

#define XCBLK             4
#define XCBLK_SZ        3  /* size in bit */

#define XPABLK    6
#define XPABLK_SZ 2

#define XPBBLK    8
#define XPBBLK_SZ 2

/**************
MCBSP_MCR1_REG
***************/

#define RMCM              0
#define RMCM_SZ         1  /* size in bit */

#define RCBLK             4
#define RCBLK_SZ        3  /* size in bit */

#define RPABLK    6
#define RPABLK_SZ 2

#define RPBBLK    8
#define RPBBLK_SZ 2

//#########################

// Reset values definition

//#########################


// Serial Port Control Register 2
//================================
#define FREE_RES_VAL      0x0  
#define SOFT_RES_VAL      0x0  
#define FRST_RES_VAL      0x0  
#define GRST_RES_VAL      0x0  
#define XINTM_RES_VAL      0x0  
#define XSYNCERR_RES_VAL  0x0  
#define XEMPTY_RES_VAL    0x0  
#define XRDY_RES_VAL      0x0  
#define XRST_RES_VAL      0x0  

// Serial Port Control Register 1
//================================
#define DLB_RES_VAL        0x0
#define RJUST_RES_VAL      0x0
#define CLKSTP_RES_VAL    0x0
#define DXENA_RES_VAL      0x0
#define ABIS_RES_VAL      0x0
#define RINTM_RES_VAL      0x0
#define RSYNCERR_RES_VAL  0x0
#define RFULL_RES_VAL      0x0
#define RRDY_RES_VAL      0x0
#define RRST_RES_VAL      0x0


// Receive Control Register 2
//============================
#define RPHASE_RES_VAL    0x0
#define RFRLEN2_RES_VAL  0x0
#define RWDLEN2_RES_VAL  0x0
#define RCOMPAND_RES_VAL  0x0
#define RFIG_RES_VAL      0x0
#define RDATDLY_RES_VAL  0x0


// Receive Control Register 1
//============================
#define RFRLEN1_RES_VAL  0x0
#define RWDLEN1_RES_VAL  0x0

// Transmit Control Register 2
//=============================
#define XPHASE_RES_VAL    0x0
#define XFRLEN2_RES_VAL   0x0
#define XWDLEN2_RES_VAL   0x0
#define XCOMPAND_RES_VAL  0x0
#define XFIG_RES_VAL      0x0
#define XDATDLY_RES_VAL   0x0

// Transmit Control Register 1
//=============================
#define XFRLEN1_RES_VAL  0x0
#define XWDLEN1_RES_VAL  0x0

// Sample Rate Generator Register 2
//==================================
#define GSYNC_RES_VAL 0x0
#define CLKSP_RES_VAL 0x0
#define CLKSM_RES_VAL 0x0
#define FSGM_RES_VAL  0x0
#define FPER_RES_VAL  0x0

// Sample Rate Generator Register 1
//==================================
#define FWID_RES_VAL    0x0
#define CLKGDV_RES_VAL  0x0


// Multi-Channel Register 2
//==========================
#define RPBBLK_RES_VAL    0x0
#define RPABLK_RES_VAL    0x0
#define RCBLK_RES_VAL     0x0
#define RMCM_RES_VAL      0x0

// Multi-Channel Register 1
//==========================
#define XPBBLK_RES_VAL    0x0
#define XPABLK_RES_VAL    0x0
#define XCBLK_RES_VAL     0x0
#define XMCM_RES_VAL      0x0


// Receive/Transmitt Channel Enable Register Partition A/B
//=========================================================
#define MCBSP_RCERA_REG_RES_VAL     0x0000
#define MCBSP_RCERB_REG_RES_VAL     0x0000
#define MCBSP_XCERA_REG_RES_VAL     0x0000
#define MCBSP_XCERB_REG_RES_VAL     0x0000

// Pin Control Register Fields
//=============================
#define XIOEN_RES_VAL       0x0  
#define RIOEN_RES_VAL       0x0  
#define FSXM_RES_VAL        0x0    
#define FSRM_RES_VAL        0x0    
#define CLKXM_RES_VAL       0x0  
#define CLKRM_RES_VAL       0x0  
#define CLKS_STAT_RES_VAL   0x0  
#define DX_STAT_RES_VAL     0x0  
#define DR_STAT_RES_VAL     0x0  
#define FSXP_RES_VAL        0x0    
#define FSRP_RES_VAL        0x0    
#define CLKXP_RES_VAL       0x0  
#define CLKRP_RES_VAL       0x0  

//#########################

/* macro definitions*/

//#########################


#define  MCBSP_TRANSMIT_ENABLE       MCBSP_LoadField(MCBSP_SPCR2_REG,  XRST_SZ  ,XRST  ,1)  
#define  MCBSP_TRANSMIT_DISABLE            MCBSP_LoadField(MCBSP_SPCR2_REG,  XRST_SZ  ,XRST  ,0)

#define  MCBSP_RECEIVE_ENABLE       MCBSP_LoadField(MCBSP_SPCR1_REG,  RRST_SZ  ,RRST  ,1)
#define  MCBSP_RECEIVE_DISABLE      MCBSP_LoadField(MCBSP_SPCR1_REG,  RRST_SZ  ,RRST  ,0)

#define  MCBSP_SAMPLE_RATE_GEN_ENABLE     MCBSP_LoadField(MCBSP_SPCR2_REG,  GRST_SZ  ,GRST  ,1)
#define  MCBSP_SAMPLE_RATE_GEN_DISABLE    MCBSP_LoadField(MCBSP_SPCR2_REG,  GRST_SZ  ,GRST  ,0)

#define  MCBSP_FRAME_SYNCHRO_GEN_ENABLE          MCBSP_LoadField(MCBSP_SPCR2_REG,  FRST_SZ  ,FRST  ,1)
#define  MCBSP_FRAME_SYNCHRO_GEN_DISABLE          MCBSP_LoadField(MCBSP_SPCR2_REG,  FRST_SZ  ,FRST  ,0)


#define  MCBSP_XINT_ON_TRANSMIT_SYNCHRO_ERROR    MCBSP_LoadField(MCBSP_SPCR2_REG,  XINTM_SZ ,XINTM  ,3) 
#define  MCBSP_RINT_ON_RECEIVE_SYNCHRO_ERROR     MCBSP_LoadField(MCBSP_SPCR1_REG,  RINTM_SZ ,RINTM  ,3)

#define  MCBSP_XINT_ON_TRANSMIT_FRAME_SYNCHRO    MCBSP_LoadField(MCBSP_SPCR2_REG,  XINTM_SZ ,XINTM  ,2) 
#define  MCBSP_RINT_ON_RECEIVE_FRAME_SYNCHRO     MCBSP_LoadField(MCBSP_SPCR1_REG,  RINTM_SZ ,RINTM  ,2)





//####################################################################################