mcbsp.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*************************************************************
   Description      : mcbsp lib header
   Project          : HELEN   
   Author           : JL MASSEAU
   Modified for HELEN by JP Ulpiano [e-mail]
**************************************************************/
#include "result.h"
#include "test.h"
#include "tb_regs.h"

#ifndef _MCBSP_H
#define _MCBSP_H
//#########################

/* mcbsp registers offset*/

//#########################


#define MCBSP_DRR2_REG_OFFSET 0x00 /* data receive register 2 */
#define MCBSP_DRR1_REG_OFFSET 0x02 /* data receive register 1 */
#define MCBSP_DXR2_REG_OFFSET 0x04 /* data transmit register 2 */
#define MCBSP_DXR1_REG_OFFSET 0x06 /* data tranmit register 1 */

#define MCBSP_SPCR2_REG_OFFSET 0x08 /* serial port control register 2 */
#define MCBSP_SPCR1_REG_OFFSET 0x0A /* serial port control register 1 */
#define MCBSP_RCR2_REG_OFFSET  0x0C /* receive control register 2 */
#define MCBSP_RCR1_REG_OFFSET  0x0E /* receive control register 1 */
#define MCBSP_XCR2_REG_OFFSET  0x10 /* transmit control register 2 */
#define MCBSP_XCR1_REG_OFFSET  0x12 /* transmit control register 1 */
#define MCBSP_SRGR2_REG_OFFSET 0x14 /* sample rate generator register 2 */
#define MCBSP_SRGR1_REG_OFFSET 0x16 /* sample rate generator register 1 */
#define MCBSP_MCR2_REG_OFFSET  0x18 /* multi channel register 2 */
#define MCBSP_MCR1_REG_OFFSET  0x1A /* multi channel register 1 */
#define MCBSP_RCERA_REG_OFFSET 0x1C /* receive channel enable register partition A */
#define MCBSP_RCERB_REG_OFFSET 0x1E /* receive channel enable register partition B */
#define MCBSP_XCERA_REG_OFFSET 0x20 /* transmit channel enable register partition A */
#define MCBSP_XCERB_REG_OFFSET 0x22 /* transmit channel enable register partition B */
#define MCBSP_PCR_REG_OFFSET   0x24 /* pin control register */

//#########################

/* mcbsp registers address*/

//#########################

#define MCBSP_DRR2_REG  (MCBSP_ADDR + MCBSP_DRR2_REG_OFFSET )
#define MCBSP_DRR1_REG  (MCBSP_ADDR + MCBSP_DRR1_REG_OFFSET )
#define MCBSP_DXR2_REG  (MCBSP_ADDR + MCBSP_DXR2_REG_OFFSET )
#define MCBSP_DXR1_REG  (MCBSP_ADDR + MCBSP_DXR1_REG_OFFSET )

#define MCBSP_SPCR2_REG (MCBSP_ADDR + MCBSP_SPCR2_REG_OFFSET )
#define MCBSP_SPCR1_REG (MCBSP_ADDR + MCBSP_SPCR1_REG_OFFSET )
#define MCBSP_RCR2_REG  (MCBSP_ADDR + MCBSP_RCR2_REG_OFFSET )
#define MCBSP_RCR1_REG  (MCBSP_ADDR + MCBSP_RCR1_REG_OFFSET )
#define MCBSP_XCR2_REG  (MCBSP_ADDR + MCBSP_XCR2_REG_OFFSET )
#define MCBSP_XCR1_REG  (MCBSP_ADDR + MCBSP_XCR1_REG_OFFSET )
#define MCBSP_SRGR2_REG (MCBSP_ADDR + MCBSP_SRGR2_REG_OFFSET )
#define MCBSP_SRGR1_REG (MCBSP_ADDR + MCBSP_SRGR1_REG_OFFSET )
#define MCBSP_MCR2_REG  (MCBSP_ADDR + MCBSP_MCR2_REG_OFFSET )
#define MCBSP_MCR1_REG  (MCBSP_ADDR + MCBSP_MCR1_REG_OFFSET )
#define MCBSP_RCERA_REG (MCBSP_ADDR + MCBSP_RCERA_REG_OFFSET )
#define MCBSP_RCERB_REG (MCBSP_ADDR + MCBSP_RCERB_REG_OFFSET )
#define MCBSP_XCERA_REG (MCBSP_ADDR + MCBSP_XCERA_REG_OFFSET )
#define MCBSP_XCERB_REG (MCBSP_ADDR + MCBSP_XCERB_REG_OFFSET )
#define MCBSP_PCR_REG   (MCBSP_ADDR + MCBSP_PCR_REG_OFFSET )

//#########################

/* mcbsp registers bit name */

//#########################

/**************
MCBSP_SPCR2_REG
***************/

#define FREE    9 /* Free Running Mode */
#define FREE_SZ    1  /* size in bit */
/*FREE = 0 Free running mode is disabled 
FREE = 1 Free running mode is enabled */

#define SOFT    8 /* Soft Bit */
#define SOFT_SZ    1  /* size in bit */
/*SOFT = 0 SOFT mode is disabled 
SOFT = 1 SOFT mode is enabled */

#define FRST    7 /* Frame-Sync Generator Reset */
#define FRST_SZ    1  /* size in bit */
/*FRST = 0 Frame-synchronization logic is reset. Frame-sync signal FSG is not generated by the sample-rate generator. 
FRST = 1 Frame-sync signal FSG is generated after (FPER+1) number of CLKG clocks; i.e., 
          all frame counters are loaded with their programmed values. */

#define GRST    6 /* Sample-Rate Generator Reset */
#define GRST_SZ    1  /* size in bit */
/*GRST =0 Sample rate generator is reset 
GRST =1 Sample rate generator is pulled out of reset. 
        CLKG is driven as per programmed value in sample rate generator registers (SRGR[1,2]).*/
  
#define XINTM    5 /* Transmit Interrupt Mode */
#define XINTM_SZ  2  /* size in bit */
/*XINTM = 00 XINT driven by XRDY (i.e., end of word) and end of frame in A-bis mode. 
XINTM = 01 XINT generated by end-of-block or end-of-frame in multichannel operation 
XINTM = 10 XINT generated by a new frame synchronization 
XINTM=11 XINT generated by XSYNCERR */

#define XSYNCERR  3  /* Transmit Synchronization Error */
#define XSYNCERR_SZ  1  /* size in bit */
/*XSYNCERR = 0 No synchronization error 
XSYNCERR = 1 Synchronization error detected by McBSP. */

#define XEMPTY    2  /* Transmit Shift Register (XSR[1,2]) Empty */
#define XEMPTY_SZ  1  /* size in bit */
/*XEMPTY =0 XSR[1,2] is empty 
XEMPTY =1 XSR[1,2] is not empty */

#define XRDY    1 /* Transmitter Ready */
#define XRDY_SZ    1  /* size in bit */
/*XRDY = 0 Transmitter is not ready. 
XRDY = 1 Transmitter is ready for new data in DXR[1,2]. */

#define XRST    0 /* Transmitter reset. This resets and enables the transmitter.*/
#define XRST_SZ    1  /* size in bit */
/*XRST =0 The serial port transmitter is disabled and in reset state. 
XRST =1 The serial port transmitter is enabled.  */

/**************  
MCBSP_SPCR1_REG
***************/

#define  DLB    15 /* DLB Digital Loop Back Mode */
#define DLB_SZ    1  /* size in bit */
/*DLB =0 Digital loop back mode disabled 
  DLB =1  Digital loop back mode enabled  */

#define RJUST    14 /*Receive Sign-Extension and Justification Mode */
#define RJUST_SZ  2  /* size in bit */
/*RJUST = 00 Right-justify and zero-fill MSBs in DRR[1,2] 
RJUST = 01 Right-justify and sign-extend MSBs in DRR[1,2] 
RJUST = 10 Left-justify and zero-fill LSBs in DRR[1,2] 
RJUST = 11 Reserved*/

#define CLKSTP    12 /* Clock Stop Mode */
#define CLKSTP_SZ  2  /* size in bit */
/*CLKSTP = 0X Clock stop mode disabled. Normal clocking for non-SPI mode. Various SPI modes when: 
CLKSTP = 10 and CLKXP = 0 Clock starts with rising edge without delay 
CLKSTP = 10 and CLKXP = 1 Clock starts with falling edge without delay 
CLKSTP = 11 and CLKXP = 0 Clock starts with rising edge with delay 
CLKSTP = 11 and CLKXP = 1 Clock starts with falling edge with delay */

#define DXENA    7  /* DX Enabler*/
#define DXENA_SZ  1  /* size in bit */
/*DXENA = 0 DX enabler is off 
DXENA = 1 DX enabler is on */

#define  ABIS    6 /* ABIS Mode */
#define ABIS_SZ    1 /* size in bit */
/*ABIS = 0 A-bis mode is disabled 
ABIS = 1 A-bis mode is enabled */

#define RINTM    5 /* Receive Interrupt Mode */
#define RINTM_SZ  2 /* size in bit */
/*RINTM = 00 RINT driven by RRDY (i.e. end of word) and end of frame in A-bis mode. 
RINTM = 01 RINT generated by end-of-block or end-of-frame in multichannel operation 
RINTM = 10 RINT generated by a new frame synchronization 
RINTM=11 RINT generated by RSYNCERR */

#define RSYNCERR  3 /*Receive Synchronization Error */
#define RSYNCERR_SZ  1 /* size in bit */
/*RSYNCERR = 0 No synchronization error 
RSYNCERR = 1 Synchronization error detected by McBSP.*/

#define RFULL    2 /*Receive Shift Register (RSR[1,2]) Full */
#define RFULL_SZ  1 /* size in bit */
/*RFULL = 0 RBR[1,2] is not in overrun condition 
RFULL = 1 DRR[1,2] is not read, RBR[1,2] is full and RSR[1,2] is also full with new word */

#define RRDY    1 /* Receiver Ready */
#define RRDY_SZ    1 /* size in bit */
/*RRDY = 0 Receiver is not ready. 
RRDY = 1 Receiver is ready with data to be read from DRR[1,2] */

#define RRST     0 /* Receiver reset. This resets and enables the receiver.*/
#define RRST_SZ    1 /* size in bit */
/*RRST =0 The serial port receiver is disabled and in reset state. 
RRST =1 The serial port receiver is enabled.*/

/**************  
MCBSP_RCR2_REG  
***************/

#define RPHASE    15 /* Receive Phases */
#define RPHASE_SZ  1  /* size in bit */
/* RPHASE = 0 Single-phase frame 
RPHASE = 1 Dual-phase frame */

#define RFRLEN2    14 /* Receive Frame Length */
#define RFRLEN2_SZ  7  /* size in bit */
/* RFRLEN2 = 000 0000 1 word per frame 
RFRLEN2 = 000 0001 2 words per frame to  
RFRLEN1 = 111 1111 128 words per frame */

#define RWDLEN2    7 /* Receive Word Length */
#define RWDLEN2_SZ  3 /* size in bit */
/* RWDLEN2 = 000 8 bits 
RWDLEN2 = 001 12 bits 
RWDLEN2 = 010 16 bits 
RWDLEN2 = 011 20 bits 
RWDLEN2 = 100 24 bits 
RWDLEN2 = 101 32 bits 
RWDLEN2 = 11X Reserved */

#define RCOMPAND    4 /* Receive companding mode.*/
#define RCOMPAND_SZ    2 /* size in bit */
/* Modes other than 00b are only enabled when the appropriate RWDLEN is 000b, indicating 8-bit data
RCOMPAND = 00 No companding, data transfer starts with MSB first. 
RCOMPAND = 01 No companding, 8-bit data, transfer starts with LSB first. 
RCOMPAND = 10 Compand using m-law for receive data. 
RCOMPAND = 11 Compand using A-law for receive data. */

#define RFIG    2 /* Receive Frame Ignore */
#define RFIG_SZ    1 /* size in bit */
/* RFIG = 0 Receive frame-synchronization pulses after the first restarts the transfer. 
RFIG = 1 Receive frame-synchronization pulses after the first are ignored. */

#define RDATDLY    1 /* Receive data delay */
#define RDATDLY_SZ  2 /* size in bit */
/* RDATDLY = 00 0-bit data delay 
RDATDLY = 01 1-bit data delay 
RDATDLY = 10 2-bit data delay 
RDATDLY = 11 Reserved*/

/**************
MCBSP_RCR1_REG  
***************/

#define RFRLEN1    14 /* Receive Frame Length */
#define RFRLEN1_SZ  7  /* size in bit */
/* RFRLEN1 = 000 0000 1 word per frame 
RFRLEN1 = 000 0001 2 words per frame to 
RFRLEN1 = 111 1111 128 words per frame */

#define RWDLEN1    7 /* Receive Word Length */
#define RWDLEN1_SZ  3 /* size in bit */
/* RWDLEN1 = 000 8 bits 
RWDLEN1 = 001 12 bits 
RWDLEN1 = 010 16 bits 
RWDLEN1 = 011 20 bits 
RWDLEN1 = 100 24 bits 
RWDLEN1 = 101 32 bits 
RWDLEN1 = 11X Reserved */

/**************
MCBSP_XCR2_REG  
***************/
#define XPHASE    15 /* Transmit Phases */
#define XPHASE_SZ  1  /* size in bit */
/* XPHASE = 0 Single-phase frame 
XPHASE = 1 Dual-phase frame */

#define XFRLEN2    14 /* Transmit Frame Length */
#define XFRLEN2_SZ  7 /* size in bit */
/* XFRLEN2 = 000 0000 1 word per frame 
XFRLEN2 = 000 0001 2 words per frame to
 XFRLEN1 = 111 1111 128 words per frame */
 
#define XWDLEN2    7 /* Transmit Word Length */
#define XWDLEN2_SZ  3 /* size in bit */
/* XWDLEN2 = 000 8 bits 
XWDLEN2 = 001 12 bits 
XWDLEN2 = 010 16 bits 
XWDLEN2 = 011 20 bits 
XWDLEN2 = 100 24 bits 
XWDLEN2 = 101 32 bits 
XWDLEN2 = 11X Reserved */

#define XCOMPAND  4 /* Transmit companding mode */
#define XCOMPAND_SZ  2 /* size in bit */
/* XCOMPAND = 00 No companding, data transfer starts with MSB first. 
XCOMPAND = 01 No companding, 8-bit data, transfer starts with LSB first. 
XCOMPAND = 10 Compand using m-law for transmit data. 
XCOMPAND = 11 Compand using A-law for transmit data. */

#define XFIG    2 /* Transmit Frame Ignore */ 
#define XFIG_SZ    1 /* size in bit */
/*XFIG = 0 Transmit frame-synchronization pulses after the first restarts the transfer. 
XFIG = 1 Transmit frame-synchronization pulses after the first are ignored. */

#define XDATDLY   1 /* Transmit Data Delay */
#define XDATDLY_SZ  2 /* size in bit */
/* XDATDLY = 00 0-bit data delay 
XDATDLY = 01 1-bit data delay 
XDATDLY = 10 2-bit data delay 
XDATDLY = 11 Reserved */

/**************
MCBSP_XCR1_REG  
***************/

#define XFRLEN1    14 /* Transmit Frame Length */
#define XFRLEN1_SZ  7  /* size in bit */
/* XFRLEN1 = 000 0000 1 word per frame 
XFRLEN1 = 000 0001 2 words per frame to
RFRLEN1 = 111 1111 128 words per frame */

#define XWDLEN1    7 /* Transmit Word Length */