timer_32k.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :timer_32k.h
//
//   Date of Module Modification:5/28/02
//   Date of Generation :8/29/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _TIMER_32K__H
#define _TIMER_32K__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            TIMER_32K_TICK_VALUE_REG_OFFSET                                                                     0x00
#define            TIMER_32K_TICK_COUNTER_REG_OFFSET                                                                   0x04
#define            TIMER_32K_TIMER_CTRL_REG_OFFSET                                                                     0x08




//TIMER_32K_TICK_VALUE_REG
//-------------------
#define            TIMER_32K_TICK_VALUE_REG                                                                            REG32(TIMER_32K_BASE_ADDR_ARM+TIMER_32K_TICK_VALUE_REG_OFFSET)


#define            TIMER_32K_TICK_VALUE_REG_RESERVED_POS                                                                 24
#define            TIMER_32K_TICK_VALUE_REG_RESERVED_NUMB                                                                8
#define            TIMER_32K_TICK_VALUE_REG_RESERVED_RES_VAL                                                             0x0
//R

#define            TIMER_32K_TICK_VALUE_REG_TVR_POS                                                                      0
#define            TIMER_32K_TICK_VALUE_REG_TVR_NUMB                                                                     24
#define            TIMER_32K_TICK_VALUE_REG_TVR_RES_VAL                                                                  0xFFFFFF
//R/W


//TIMER_32K_TICK_COUNTER_REG
//-------------------
#define            TIMER_32K_TICK_COUNTER_REG                                                                          REG32(TIMER_32K_BASE_ADDR_ARM+TIMER_32K_TICK_COUNTER_REG_OFFSET)


#define            TIMER_32K_TICK_COUNTER_REG_RESERVED_POS                                                               24
#define            TIMER_32K_TICK_COUNTER_REG_RESERVED_NUMB                                                              8
#define            TIMER_32K_TICK_COUNTER_REG_RESERVED_RES_VAL                                                           0x0
//R

#define            TIMER_32K_TICK_COUNTER_REG_TCR_POS                                                                    0
#define            TIMER_32K_TICK_COUNTER_REG_TCR_NUMB                                                                   24
#define            TIMER_32K_TICK_COUNTER_REG_TCR_RES_VAL                                                                0xFFFFFF
//R


//TIMER_32K_TIMER_CTRL_REG
//-------------------
#define            TIMER_32K_TIMER_CTRL_REG                                                                            REG32(TIMER_32K_BASE_ADDR_ARM+TIMER_32K_TIMER_CTRL_REG_OFFSET)


#define            TIMER_32K_TIMER_CTRL_REG_RESERVED_POS                                                                 4
#define            TIMER_32K_TIMER_CTRL_REG_RESERVED_NUMB                                                                28
#define            TIMER_32K_TIMER_CTRL_REG_RESERVED_RES_VAL                                                             0x0
//R

#define            TIMER_32K_TIMER_CTRL_REG_ARL_POS                                                                      3
#define            TIMER_32K_TIMER_CTRL_REG_ARL_NUMB                                                                     1
#define            TIMER_32K_TIMER_CTRL_REG_ARL_RES_VAL                                                                  0x1
//R/W

#define            TIMER_32K_TIMER_CTRL_REG_IT_ENA_POS                                                                   2
#define            TIMER_32K_TIMER_CTRL_REG_IT_ENA_NUMB                                                                  1
#define            TIMER_32K_TIMER_CTRL_REG_IT_ENA_RES_VAL                                                               0x0
//R/W

#define            TIMER_32K_TIMER_CTRL_REG_TRB_POS                                                                      1
#define            TIMER_32K_TIMER_CTRL_REG_TRB_NUMB                                                                     1
#define            TIMER_32K_TIMER_CTRL_REG_TRB_RES_VAL                                                                  0x0
//R/W

#define            TIMER_32K_TIMER_CTRL_REG_TSS_POS                                                                      0
#define            TIMER_32K_TIMER_CTRL_REG_TSS_NUMB                                                                     1
#define            TIMER_32K_TIMER_CTRL_REG_TSS_RES_VAL                                                                  0x0
//R/W

#endif