llpc.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//LLPC_LEVEL_ACTIVITY_CONTROL
//-------------------
#define            LLPC_LEVEL_ACTIVITY_CONTROL                                                                         REG16(LLPC_BASE_ADDR_ARM+LLPC_LEVEL_ACTIVITY_CONTROL_OFFSET)


#define            LLPC_LEVEL_ACTIVITY_CONTROL_HS_VS_ACTIVE_LEVEL_POS                                                    5
#define            LLPC_LEVEL_ACTIVITY_CONTROL_HS_VS_ACTIVE_LEVEL_NUMB                                                   1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_HS_VS_ACTIVE_LEVEL_RES_VAL                                                0x0
//R/W

#define            LLPC_LEVEL_ACTIVITY_CONTROL_PIXEL_SUSP_LEVEL_POS                                                      4
#define            LLPC_LEVEL_ACTIVITY_CONTROL_PIXEL_SUSP_LEVEL_NUMB                                                     1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_PIXEL_SUSP_LEVEL_RES_VAL                                                  0x0
//R/W

#define            LLPC_LEVEL_ACTIVITY_CONTROL_PCLK_SUSP_LEVEL_POS                                                       3
#define            LLPC_LEVEL_ACTIVITY_CONTROL_PCLK_SUSP_LEVEL_NUMB                                                      1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_PCLK_SUSP_LEVEL_RES_VAL                                                   0x0
//R/W

#define            LLPC_LEVEL_ACTIVITY_CONTROL_OE_SUSP_LEVEL_POS                                                         2
#define            LLPC_LEVEL_ACTIVITY_CONTROL_OE_SUSP_LEVEL_NUMB                                                        1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_OE_SUSP_LEVEL_RES_VAL                                                     0x0
//R/W

#define            LLPC_LEVEL_ACTIVITY_CONTROL_HS_SUSP_LEVEL_POS                                                         1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_HS_SUSP_LEVEL_NUMB                                                        1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_HS_SUSP_LEVEL_RES_VAL                                                     0x0
//R/W

#define            LLPC_LEVEL_ACTIVITY_CONTROL_VS_SUSP_LEVEL_POS                                                         0
#define            LLPC_LEVEL_ACTIVITY_CONTROL_VS_SUSP_LEVEL_NUMB                                                        1
#define            LLPC_LEVEL_ACTIVITY_CONTROL_VS_SUSP_LEVEL_RES_VAL                                                     0x0
//R/W


//LLPC_HFP_HBP
//-------------------
#define            LLPC_HFP_HBP                                                                                        REG16(LLPC_BASE_ADDR_ARM+LLPC_HFP_HBP_OFFSET)


#define            LLPC_HFP_HBP_HFP_POS                                                                                  8
#define            LLPC_HFP_HBP_HFP_NUMB                                                                                 8
#define            LLPC_HFP_HBP_HFP_RES_VAL                                                                              0xFF
//R/W

#define            LLPC_HFP_HBP_HBP_POS                                                                                  0
#define            LLPC_HFP_HBP_HBP_NUMB                                                                                 8
#define            LLPC_HFP_HBP_HBP_RES_VAL                                                                              0xFF
//R/W


//LLPC_VFP_VBP
//-------------------
#define            LLPC_VFP_VBP                                                                                        REG16(LLPC_BASE_ADDR_ARM+LLPC_VFP_VBP_OFFSET)


#define            LLPC_VFP_VBP_VFP_POS                                                                                  8
#define            LLPC_VFP_VBP_VFP_NUMB                                                                                 8
#define            LLPC_VFP_VBP_VFP_RES_VAL                                                                              0x01
//R/W

#define            LLPC_VFP_VBP_VBP_POS                                                                                  0
#define            LLPC_VFP_VBP_VBP_NUMB                                                                                 8
#define            LLPC_VFP_VBP_VBP_RES_VAL                                                                              0x01
//R/W


//LLPC_VSYNC_INTERRUPT
//-------------------
#define            LLPC_VSYNC_INTERRUPT                                                                                REG16(LLPC_BASE_ADDR_ARM+LLPC_VSYNC_INTERRUPT_OFFSET)


#define            LLPC_VSYNC_INTERRUPT_INT_MODE_POS                                                                     9
#define            LLPC_VSYNC_INTERRUPT_INT_MODE_NUMB                                                                    1
#define            LLPC_VSYNC_INTERRUPT_INT_MODE_RES_VAL                                                                 0x0
//R/W

#define            LLPC_VSYNC_INTERRUPT_VS_INT_ENA_POS                                                                   8
#define            LLPC_VSYNC_INTERRUPT_VS_INT_ENA_NUMB                                                                  1
#define            LLPC_VSYNC_INTERRUPT_VS_INT_ENA_RES_VAL                                                               0x0
//R/W

#define            LLPC_VSYNC_INTERRUPT_NUM_VS_WAIT_IT_POS                                                               0
#define            LLPC_VSYNC_INTERRUPT_NUM_VS_WAIT_IT_NUMB                                                              8
#define            LLPC_VSYNC_INTERRUPT_NUM_VS_WAIT_IT_RES_VAL                                                           0xFF
//R/W


//LLPC_VSYNC_OE_STATUS
//-------------------
#define            LLPC_VSYNC_OE_STATUS                                                                                REG16(LLPC_BASE_ADDR_ARM+LLPC_VSYNC_OE_STATUS_OFFSET)


#define            LLPC_VSYNC_OE_STATUS_VALUE_VS_OUT_POS                                                                 1
#define            LLPC_VSYNC_OE_STATUS_VALUE_VS_OUT_NUMB                                                                1
#define            LLPC_VSYNC_OE_STATUS_VALUE_VS_OUT_RES_VAL                                                             0x0
//R

#define            LLPC_VSYNC_OE_STATUS_VALUE_OE_OUT_POS                                                                 0
#define            LLPC_VSYNC_OE_STATUS_VALUE_OE_OUT_NUMB                                                                1
#define            LLPC_VSYNC_OE_STATUS_VALUE_OE_OUT_RES_VAL                                                             0x0
//R


//LLPC_CLK_MODE
//-------------------
#define            LLPC_CLK_MODE                                                                                       REG16(LLPC_BASE_ADDR_ARM+LLPC_CLK_MODE_OFFSET)


#define            LLPC_CLK_MODE_CLK13M_REQ_POS                                                                          0
#define            LLPC_CLK_MODE_CLK13M_REQ_NUMB                                                                         1
#define            LLPC_CLK_MODE_CLK13M_REQ_RES_VAL                                                                      0x0
//R/W


//LLPC_OE_EVENT
//-------------------
#define            LLPC_OE_EVENT                                                                                       REG16(LLPC_BASE_ADDR_ARM+LLPC_OE_EVENT_OFFSET)


#define            LLPC_OE_EVENT_OE_FALLEDGE_IT_ENA_POS                                                                  0
#define            LLPC_OE_EVENT_OE_FALLEDGE_IT_ENA_NUMB                                                                 1
#define            LLPC_OE_EVENT_OE_FALLEDGE_IT_ENA_RES_VAL                                                              0x0
//R/W

#define            LLPC_OE_EVENT_OE_RISEDGE_IT_ENA_POS                                                                   1
#define            LLPC_OE_EVENT_OE_RISEDGE_IT_ENA_NUMB                                                                  1
#define            LLPC_OE_EVENT_OE_RISEDGE_IT_ENA_RES_VAL                                                               0x0
//R/W

#endif