llpc.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :perseus2_llpc.h
//
//   Date of Module Modification:7/12/02
//   Date of Generation :7/15/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _LLPC__H
#define _LLPC__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            LLPC_LLPC_OFF_PERIOD_OFFSET                                                                         0x00
#define            LLPC_LLPC_ON_PERIOD_OFFSET                                                                          0x02
#define            LLPC_LLPC_MODE_SUSPEND_SIG_OFFSET                                                                   0x04
#define            LLPC_HSW_PPL_OFFSET                                                                                 0x06
#define            LLPC_VSW_LPP_OFFSET                                                                                 0x08
#define            LLPC_LEVEL_ACTIVITY_CONTROL_OFFSET                                                                  0x0A
#define            LLPC_HFP_HBP_OFFSET                                                                                 0x0C
#define            LLPC_VFP_VBP_OFFSET                                                                                 0x0E
#define            LLPC_VSYNC_INTERRUPT_OFFSET                                                                         0x10
#define            LLPC_VSYNC_OE_STATUS_OFFSET                                                                         0x12
#define            LLPC_CLK_MODE_OFFSET                                                                                0x14
#define            LLPC_OE_EVENT_OFFSET                                                                                0x16




//LLPC_LLPC_OFF_PERIOD
//-------------------
#define            LLPC_LLPC_OFF_PERIOD                                                                                REG16(LLPC_BASE_ADDR_ARM+LLPC_LLPC_OFF_PERIOD_OFFSET)


#define            LLPC_LLPC_OFF_PERIOD_NUM_VS_OFF_POS                                                                   0
#define            LLPC_LLPC_OFF_PERIOD_NUM_VS_OFF_NUMB                                                                  8
#define            LLPC_LLPC_OFF_PERIOD_NUM_VS_OFF_RES_VAL                                                               0xFF
//R/W


//LLPC_LLPC_ON_PERIOD
//-------------------
#define            LLPC_LLPC_ON_PERIOD                                                                                 REG16(LLPC_BASE_ADDR_ARM+LLPC_LLPC_ON_PERIOD_OFFSET)


#define            LLPC_LLPC_ON_PERIOD_NUM_VS_ON_POS                                                                     0
#define            LLPC_LLPC_ON_PERIOD_NUM_VS_ON_NUMB                                                                    8
#define            LLPC_LLPC_ON_PERIOD_NUM_VS_ON_RES_VAL                                                                 0xFF
//R/W


//LLPC_LLPC_MODE_SUSPEND_SIG
//-------------------
#define            LLPC_LLPC_MODE_SUSPEND_SIG                                                                          REG16(LLPC_BASE_ADDR_ARM+LLPC_LLPC_MODE_SUSPEND_SIG_OFFSET)


#define            LLPC_LLPC_MODE_SUSPEND_SIG_MODE_POS                                                                   5
#define            LLPC_LLPC_MODE_SUSPEND_SIG_MODE_NUMB                                                                  2
#define            LLPC_LLPC_MODE_SUSPEND_SIG_MODE_RES_VAL                                                               0x0
//R/W

#define            LLPC_LLPC_MODE_SUSPEND_SIG_PIXEL_OUT_SUSP_POS                                                         4
#define            LLPC_LLPC_MODE_SUSPEND_SIG_PIXEL_OUT_SUSP_NUMB                                                        1
#define            LLPC_LLPC_MODE_SUSPEND_SIG_PIXEL_OUT_SUSP_RES_VAL                                                     0x0
//R/W

#define            LLPC_LLPC_MODE_SUSPEND_SIG_PCLK_OUT_SUSP_POS                                                          3
#define            LLPC_LLPC_MODE_SUSPEND_SIG_PCLK_OUT_SUSP_NUMB                                                         1
#define            LLPC_LLPC_MODE_SUSPEND_SIG_PCLK_OUT_SUSP_RES_VAL                                                      0x0
//R/W

#define            LLPC_LLPC_MODE_SUSPEND_SIG_OE_OUT_SUSP_POS                                                            2
#define            LLPC_LLPC_MODE_SUSPEND_SIG_OE_OUT_SUSP_NUMB                                                           1
#define            LLPC_LLPC_MODE_SUSPEND_SIG_OE_OUT_SUSP_RES_VAL                                                        0x0
//R/W

#define            LLPC_LLPC_MODE_SUSPEND_SIG_HS_OUT_SUSP_POS                                                            1
#define            LLPC_LLPC_MODE_SUSPEND_SIG_HS_OUT_SUSP_NUMB                                                           1
#define            LLPC_LLPC_MODE_SUSPEND_SIG_HS_OUT_SUSP_RES_VAL                                                        0x0
//R/W

#define            LLPC_LLPC_MODE_SUSPEND_SIG_VS_OUT_SUSP_POS                                                            0
#define            LLPC_LLPC_MODE_SUSPEND_SIG_VS_OUT_SUSP_NUMB                                                           1
#define            LLPC_LLPC_MODE_SUSPEND_SIG_VS_OUT_SUSP_RES_VAL                                                        0x0
//R/W


//LLPC_HSW_PPL
//-------------------
#define            LLPC_HSW_PPL                                                                                        REG16(LLPC_BASE_ADDR_ARM+LLPC_HSW_PPL_OFFSET)


#define            LLPC_HSW_PPL_HSW_POS                                                                                  10
#define            LLPC_HSW_PPL_HSW_NUMB                                                                                 6
// seb modif
//#define            LLPC_HSW_PPL_HSW_RES_VAL                                                                              0xFF
#define            LLPC_HSW_PPL_HSW_RES_VAL                                                                              0x3F
//R/W

#define            LLPC_HSW_PPL_PPL_POS                                                                                  0
#define            LLPC_HSW_PPL_PPL_NUMB                                                                                 10
// seb modif
//#define            LLPC_HSW_PPL_PPL_RES_VAL                                                                              0xFF
#define            LLPC_HSW_PPL_PPL_RES_VAL                                                                              0x3FF
//R/W


//LLPC_VSW_LPP
//-------------------
#define            LLPC_VSW_LPP                                                                                        REG16(LLPC_BASE_ADDR_ARM+LLPC_VSW_LPP_OFFSET)


#define            LLPC_VSW_LPP_VSW_POS                                                                                  10
#define            LLPC_VSW_LPP_VSW_NUMB                                                                                 6
#define            LLPC_VSW_LPP_VSW_RES_VAL                                                                              0x01

//R/W

#define            LLPC_VSW_LPP_LPP_POS                                                                                  0
#define            LLPC_VSW_LPP_LPP_NUMB                                                                                 10
#define            LLPC_VSW_LPP_LPP_RES_VAL                                                                              0x3FF
//R/W