📄 vlynq2ocp.h
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//R
#define VLYNQ2OCP_VLYNQR_STATUS_SWIDTH_POS 24
#define VLYNQ2OCP_VLYNQR_STATUS_SWIDTH_NUMB 3
#define VLYNQ2OCP_VLYNQR_STATUS_SWIDTH_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_MODESUP_POS 21
#define VLYNQ2OCP_VLYNQR_STATUS_MODESUP_NUMB 3
#define VLYNQ2OCP_VLYNQR_STATUS_MODESUP_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_RESERVED_1_POS 12
#define VLYNQ2OCP_VLYNQR_STATUS_RESERVED_1_NUMB 9
#define VLYNQ2OCP_VLYNQR_STATUS_RESERVED_1_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_TERROR_POS 11
#define VLYNQ2OCP_VLYNQR_STATUS_TERROR_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_TERROR_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_IFLOW_POS 10
#define VLYNQ2OCP_VLYNQR_STATUS_IFLOW_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_IFLOW_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_OFLOW_POS 9
#define VLYNQ2OCP_VLYNQR_STATUS_OFLOW_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_OFLOW_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_RERROR_POS 8
#define VLYNQ2OCP_VLYNQR_STATUS_RERROR_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_RERROR_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_LERROR_POS 7
#define VLYNQ2OCP_VLYNQR_STATUS_LERROR_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_LERROR_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY3_POS 6
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY3_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY3_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY2_POS 5
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY2_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY2_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY1_POS 4
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY1_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY1_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY0_POS 3
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY0_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_NFEMPTY0_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_SPEND_POS 2
#define VLYNQ2OCP_VLYNQR_STATUS_SPEND_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_SPEND_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_MPEND_POS 1
#define VLYNQ2OCP_VLYNQR_STATUS_MPEND_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_MPEND_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQR_STATUS_LINK_POS 0
#define VLYNQ2OCP_VLYNQR_STATUS_LINK_NUMB 1
#define VLYNQ2OCP_VLYNQR_STATUS_LINK_RES_VAL 0x0
//R
//VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR
//-------------------
#define VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR_OFFSET)
#define VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR_INTCLR_POS 0
#define VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR_INTCLR_NUMB 32
#define VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR_INTCLR_RES_VAL 0x0
//R/W
//VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET
//-------------------
#define VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET_OFFSET)
#define VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET_INTSET_POS 0
#define VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET_INTSET_NUMB 32
#define VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET_INTSET_RES_VAL 0x0
//R/W
//VLYNQ2OCP_VLYNQR_IRQ_POINTER
//-------------------
#define VLYNQ2OCP_VLYNQR_IRQ_POINTER REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_IRQ_POINTER_OFFSET)
#define VLYNQ2OCP_VLYNQR_IRQ_POINTER_INTPTR_POS 0
#define VLYNQ2OCP_VLYNQR_IRQ_POINTER_INTPTR_NUMB 32
#define VLYNQ2OCP_VLYNQR_IRQ_POINTER_INTPTR_RES_VAL 0x0
//R/W
//VLYNQ2OCP_VLYNQR_TX_ADDR_MAP
//-------------------
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_OFFSET)
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_TXADRMAP_POS 2
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_TXADRMAP_NUMB 30
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_TXADRMAP_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_RESERVED_POS 0
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_RESERVED_NUMB 2
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_RESERVED_RES_VAL 0x0
//R
//VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1
//-------------------
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1 REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_OFFSET)
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_RXADRSIZE1_POS 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_RXADRSIZE1_NUMB 30
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_RXADRSIZE1_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_RESERVED_POS 0
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_RESERVED_NUMB 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_RESERVED_RES_VAL 0x0
//R
//VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1
//-------------------
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1 REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_OFFSET)
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_RXADROFFSET1_POS 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_RXADROFFSET1_NUMB 30
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_RXADROFFSET1_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_RESERVED_POS 0
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_RESERVED_NUMB 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_RESERVED_RES_VAL 0x0
//R
//VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2
//-------------------
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2 REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_OFFSET)
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_RXADRSIZE2_POS 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_RXADRSIZE2_NUMB 30
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_RXADRSIZE2_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_RESERVED_POS 0
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_RESERVED_NUMB 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_RESERVED_RES_VAL 0x0
//R
//VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET2
//-------------------
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET2 REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET2_OFFSET)
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET2_RXADROFFSET2_POS 2
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET2_RXADROFFSET2_NUMB ⌨️ 快捷键说明
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