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📄 vlynq2ocp.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL7_POS                                                             29
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL7_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL7_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC7_POS                                                             24
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC7_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC7_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN6_POS                                                              23
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN6_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN6_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE6_POS                                                            22
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE6_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE6_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL6_POS                                                             21
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL6_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL6_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC6_POS                                                             16
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC6_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC6_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN5_POS                                                              15
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN5_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN5_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE5_POS                                                            14
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE5_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE5_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL5_POS                                                             13
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL5_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL5_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC5_POS                                                             8
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC5_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC5_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN4_POS                                                              7
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN4_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN4_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE4_POS                                                            6
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE4_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE4_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL4_POS                                                             5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL4_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTPOL4_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC4_POS                                                             0
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC4_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTVEC4_RES_VAL                                                         0x0
//R/W


//VLYNQ2OCP_VLYNQR_REV_ID_REG
//-------------------
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG                                                                         REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_REV_ID_REG_OFFSET)


#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_ID_POS                                                                    16
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_ID_NUMB                                                                   16
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_ID_RES_VAL                                                                0x1
//R

#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_REVMAJ_POS                                                                8
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_REVMAJ_NUMB                                                               8
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_REVMAJ_RES_VAL                                                            0x1
//R

#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_REVMIN_POS                                                                0
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_REVMIN_NUMB                                                               8
#define            VLYNQ2OCP_VLYNQR_REV_ID_REG_REVMIN_RES_VAL                                                            0x0A
//R


//VLYNQ2OCP_VLYNQR_CONTROL
//-------------------
#define            VLYNQ2OCP_VLYNQR_CONTROL                                                                            REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_CONTROL_OFFSET)


#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_0_POS                                                               24
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_0_NUMB                                                              8
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_0_RES_VAL                                                           0x0
//R

#define            VLYNQ2OCP_VLYNQR_CONTROL_MODE_POS                                                                     21
#define            VLYNQ2OCP_VLYNQR_CONTROL_MODE_NUMB                                                                    3
#define            VLYNQ2OCP_VLYNQR_CONTROL_MODE_RES_VAL                                                                 0x0
//R

#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_1_POS                                                               19
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_1_NUMB                                                              2
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_1_RES_VAL                                                           0x0
//R

#define            VLYNQ2OCP_VLYNQR_CONTROL_CLKDIV_POS                                                                   16
#define            VLYNQ2OCP_VLYNQR_CONTROL_CLKDIV_NUMB                                                                  3
#define            VLYNQ2OCP_VLYNQR_CONTROL_CLKDIV_RES_VAL                                                               0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_CLKDIR_POS                                                                   15
#define            VLYNQ2OCP_VLYNQR_CONTROL_CLKDIR_NUMB                                                                  1
#define            VLYNQ2OCP_VLYNQR_CONTROL_CLKDIR_RES_VAL                                                               0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_INTLOCAL_POS                                                                 14
#define            VLYNQ2OCP_VLYNQR_CONTROL_INTLOCAL_NUMB                                                                1
#define            VLYNQ2OCP_VLYNQR_CONTROL_INTLOCAL_RES_VAL                                                             0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_INTENABLE_POS                                                                13
#define            VLYNQ2OCP_VLYNQR_CONTROL_INTENABLE_NUMB                                                               1
#define            VLYNQ2OCP_VLYNQR_CONTROL_INTENABLE_RES_VAL                                                            0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_INTVEC_POS                                                                   8
#define            VLYNQ2OCP_VLYNQR_CONTROL_INTVEC_NUMB                                                                  5
#define            VLYNQ2OCP_VLYNQR_CONTROL_INTVEC_RES_VAL                                                               0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_INT2CFG_POS                                                                  7
#define            VLYNQ2OCP_VLYNQR_CONTROL_INT2CFG_NUMB                                                                 1
#define            VLYNQ2OCP_VLYNQR_CONTROL_INT2CFG_RES_VAL                                                              0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_2_POS                                                               5
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_2_NUMB                                                              2
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESERVED_2_RES_VAL                                                           0x0
//R

#define            VLYNQ2OCP_VLYNQR_CONTROL_BENDIAN_POS                                                                  4
#define            VLYNQ2OCP_VLYNQR_CONTROL_BENDIAN_NUMB                                                                 1
#define            VLYNQ2OCP_VLYNQR_CONTROL_BENDIAN_RES_VAL                                                              0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_QIDLE_POS                                                                    3
#define            VLYNQ2OCP_VLYNQR_CONTROL_QIDLE_NUMB                                                                   1
#define            VLYNQ2OCP_VLYNQR_CONTROL_QIDLE_RES_VAL                                                                0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_ADROP_POS                                                                    2
#define            VLYNQ2OCP_VLYNQR_CONTROL_ADROP_NUMB                                                                   1
#define            VLYNQ2OCP_VLYNQR_CONTROL_ADROP_RES_VAL                                                                0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_ILOOP_POS                                                                    1
#define            VLYNQ2OCP_VLYNQR_CONTROL_ILOOP_NUMB                                                                   1
#define            VLYNQ2OCP_VLYNQR_CONTROL_ILOOP_RES_VAL                                                                0x0
//R/W

#define            VLYNQ2OCP_VLYNQR_CONTROL_RESET_POS                                                                    0
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESET_NUMB                                                                   1
#define            VLYNQ2OCP_VLYNQR_CONTROL_RESET_RES_VAL                                                                0x0
//R/W


//VLYNQ2OCP_VLYNQR_STATUS
//-------------------
#define            VLYNQ2OCP_VLYNQR_STATUS                                                                             REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQR_STATUS_OFFSET)


#define            VLYNQ2OCP_VLYNQR_STATUS_DEBUG_POS                                                                     29
#define            VLYNQ2OCP_VLYNQR_STATUS_DEBUG_NUMB                                                                    3
#define            VLYNQ2OCP_VLYNQR_STATUS_DEBUG_RES_VAL                                                                 0x0
//R

#define            VLYNQ2OCP_VLYNQR_STATUS_RESERVED_0_POS                                                                27
#define            VLYNQ2OCP_VLYNQR_STATUS_RESERVED_0_NUMB                                                               2
#define            VLYNQ2OCP_VLYNQR_STATUS_RESERVED_0_RES_VAL                                                            0x0

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