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📄 vlynq2ocp.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET2_RESERVED_NUMB                                                         2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET2_RESERVED_RES_VAL                                                      0x0
//R


//VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3
//-------------------
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3                                                                       REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_OFFSET)


#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_RXADRSIZE3_POS                                                          2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_RXADRSIZE3_NUMB                                                         30
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_RXADRSIZE3_RES_VAL                                                      0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_RESERVED_POS                                                            0
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_RESERVED_NUMB                                                           2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_RESERVED_RES_VAL                                                        0x0
//R


//VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3
//-------------------
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3                                                                     REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_OFFSET)


#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_RXADROFFSET3_POS                                                      2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_RXADROFFSET3_NUMB                                                     30
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_RXADROFFSET3_RES_VAL                                                  0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_RESERVED_POS                                                          0
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_RESERVED_NUMB                                                         2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_RESERVED_RES_VAL                                                      0x0
//R


//VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4
//-------------------
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4                                                                       REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_OFFSET)


#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_RXADRSIZE4_POS                                                          2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_RXADRSIZE4_NUMB                                                         30
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_RXADRSIZE4_RES_VAL                                                      0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_RESERVED_POS                                                            0
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_RESERVED_NUMB                                                           2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_RESERVED_RES_VAL                                                        0x0
//R


//VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4
//-------------------
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4                                                                     REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_OFFSET)


#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_RXADROFFSET4_POS                                                      2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_RXADROFFSET4_NUMB                                                     30
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_RXADROFFSET4_RES_VAL                                                  0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_RESERVED_POS                                                          0
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_RESERVED_NUMB                                                         2
#define            VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_RESERVED_RES_VAL                                                      0x0
//R


//VLYNQ2OCP_VLYNQ_CHIP_VERSION
//-------------------
#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION                                                                        REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_CHIP_VERSION_OFFSET)


#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION_DEVREV_POS                                                               16
#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION_DEVREV_NUMB                                                              16
#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION_DEVREV_RES_VAL                                                           0x0
//R

#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION_DEVID_POS                                                                0
#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION_DEVID_NUMB                                                               16
#define            VLYNQ2OCP_VLYNQ_CHIP_VERSION_DEVID_RES_VAL                                                            0x0E
//R


//VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0
//-------------------
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0                                                                       REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_OFFSET)


#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN3_POS                                                              31
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN3_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN3_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE3_POS                                                            30
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE3_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE3_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL3_POS                                                             29
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL3_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL3_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC3_POS                                                             24
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC3_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC3_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN2_POS                                                              23
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN2_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN2_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE2_POS                                                            22
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE2_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE2_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL2_POS                                                             21
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL2_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL2_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC2_POS                                                             16
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC2_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC2_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN1_POS                                                              15
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN1_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN1_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE1_POS                                                            14
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE1_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE1_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL1_POS                                                             13
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL1_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL1_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC1_POS                                                             8
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC1_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC1_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN0_POS                                                              7
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN0_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTEN0_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE0_POS                                                            6
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE0_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTTYPE0_RES_VAL                                                        0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL0_POS                                                             5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL0_NUMB                                                            1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTPOL0_RES_VAL                                                         0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC0_POS                                                             0
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC0_NUMB                                                            5
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_INTVEC0_RES_VAL                                                         0x0
//R/W


//VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4
//-------------------
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4                                                                       REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_OFFSET)


#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN7_POS                                                              31
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN7_NUMB                                                             1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTEN7_RES_VAL                                                          0x0
//R/W

#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE7_POS                                                            30
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE7_NUMB                                                           1
#define            VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_INTTYPE7_RES_VAL                                                        0x0
//R/W

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