📄 vlynq2ocp.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :vlynq2ocp.h
//
// Date of Module Modification:8/29/02
// Date of Generation :8/29/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _VLYNQ2OCP__H
#define _VLYNQ2OCP__H
//BEGIN INC GENERATION
//--------------------------------------
#define VLYNQ2OCP_BASE_ADDR_ARM 0x30002000
//Register Offset
//-------------------
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_OFFSET 0x000
#define VLYNQ2OCP_VLYNQ_CONTROL_OFFSET 0x004
#define VLYNQ2OCP_VLYNQ_STATUS_OFFSET 0x008
#define VLYNQ2OCP_VLYNQ_IRQ_STATUS_CLR_OFFSET 0x010
#define VLYNQ2OCP_VLYNQ_IRQ_PENDING_SET_OFFSET 0x014
#define VLYNQ2OCP_VLYNQ_IRQ_POINTER_OFFSET 0x018
#define VLYNQ2OCP_VLYNQ_TX_ADDR_MAP_OFFSET 0x01c
#define VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE1_OFFSET 0x020
#define VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET1_OFFSET 0x024
#define VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE2_OFFSET 0x028
#define VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET2_OFFSET 0x02c
#define VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE3_OFFSET 0x030
#define VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET3_OFFSET 0x034
#define VLYNQ2OCP_VLYNQ_RX_ADDR_SIZE4_OFFSET 0x038
#define VLYNQ2OCP_VLYNQ_RX_ADDR_OFFSET4_OFFSET 0x03c
#define VLYNQ2OCP_VLYNQ_CHIP_VERSION_OFFSET 0x040
#define VLYNQ2OCP_VLYNQ_IRQ_VECTOR3_0_OFFSET 0x060
#define VLYNQ2OCP_VLYNQ_IRQ_VECTOR7_4_OFFSET 0x064
#define VLYNQ2OCP_VLYNQR_REV_ID_REG_OFFSET 0x080
#define VLYNQ2OCP_VLYNQR_CONTROL_OFFSET 0x084
#define VLYNQ2OCP_VLYNQR_STATUS_OFFSET 0x088
#define VLYNQ2OCP_VLYNQR_IRQ_STATUS_CLR_OFFSET 0x090
#define VLYNQ2OCP_VLYNQR_IRQ_PENDING_SET_OFFSET 0x094
#define VLYNQ2OCP_VLYNQR_IRQ_POINTER_OFFSET 0x098
#define VLYNQ2OCP_VLYNQR_TX_ADDR_MAP_OFFSET 0x09c
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE1_OFFSET 0x0a0
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET1_OFFSET 0x0a4
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE2_OFFSET 0x0a8
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET2_OFFSET 0x0ac
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE3_OFFSET 0x0b0
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET3_OFFSET 0x0b4
#define VLYNQ2OCP_VLYNQR_RX_ADDR_SIZE4_OFFSET 0x0b8
#define VLYNQ2OCP_VLYNQR_RX_ADDR_OFFSET4_OFFSET 0x0bc
#define VLYNQ2OCP_VLYNQR_CHIP_VERSION_OFFSET 0x0c0
#define VLYNQ2OCP_VLYNQR_IRQ_VECTOR3_0_OFFSET 0x0e0
#define VLYNQ2OCP_VLYNQR_IRQ_VECTOR7_4_OFFSET 0x0e4
#define VLYNQ2OCP_V2O_CONFIG_OFFSET 0x100
#define VLYNQ2OCP_V2O_ADDR_FAULT_OFFSET 0x104
#define VLYNQ2OCP_VLYNQ_BUSY_OFFSET 0x108
#define VLYNQ2OCP_V2O_DMAREQ_EN_OFFSET 0x10C
//VLYNQ2OCP_VLYNQ_REV_ID_REG
//-------------------
#define VLYNQ2OCP_VLYNQ_REV_ID_REG REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_REV_ID_REG_OFFSET)
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_ID_POS 16
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_ID_NUMB 16
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_ID_RES_VAL 0x1
//R
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_REVMAJ_POS 8
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_REVMAJ_NUMB 8
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_REVMAJ_RES_VAL 0x1
//R
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_REVMIN_POS 0
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_REVMIN_NUMB 8
#define VLYNQ2OCP_VLYNQ_REV_ID_REG_REVMIN_RES_VAL 0x0A
//R
//VLYNQ2OCP_VLYNQ_CONTROL
//-------------------
#define VLYNQ2OCP_VLYNQ_CONTROL REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_CONTROL_OFFSET)
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_0_POS 24
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_0_NUMB 8
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_0_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQ_CONTROL_MODE_POS 21
#define VLYNQ2OCP_VLYNQ_CONTROL_MODE_NUMB 3
#define VLYNQ2OCP_VLYNQ_CONTROL_MODE_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_1_POS 19
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_1_NUMB 2
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_1_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQ_CONTROL_CLKDIV_POS 16
#define VLYNQ2OCP_VLYNQ_CONTROL_CLKDIV_NUMB 3
#define VLYNQ2OCP_VLYNQ_CONTROL_CLKDIV_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_CLKDIR_POS 15
#define VLYNQ2OCP_VLYNQ_CONTROL_CLKDIR_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_CLKDIR_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_INTLOCAL_POS 14
#define VLYNQ2OCP_VLYNQ_CONTROL_INTLOCAL_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_INTLOCAL_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_INTENABLE_POS 13
#define VLYNQ2OCP_VLYNQ_CONTROL_INTENABLE_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_INTENABLE_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_INTVEC_POS 8
#define VLYNQ2OCP_VLYNQ_CONTROL_INTVEC_NUMB 5
#define VLYNQ2OCP_VLYNQ_CONTROL_INTVEC_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_INT2CFG_POS 7
#define VLYNQ2OCP_VLYNQ_CONTROL_INT2CFG_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_INT2CFG_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_2_POS 5
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_2_NUMB 2
#define VLYNQ2OCP_VLYNQ_CONTROL_RESERVED_2_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQ_CONTROL_BENDIAN_POS 4
#define VLYNQ2OCP_VLYNQ_CONTROL_BENDIAN_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_BENDIAN_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_QIDLE_POS 3
#define VLYNQ2OCP_VLYNQ_CONTROL_QIDLE_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_QIDLE_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_ADROP_POS 2
#define VLYNQ2OCP_VLYNQ_CONTROL_ADROP_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_ADROP_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_ILOOP_POS 1
#define VLYNQ2OCP_VLYNQ_CONTROL_ILOOP_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_ILOOP_RES_VAL 0x0
//R/W
#define VLYNQ2OCP_VLYNQ_CONTROL_RESET_POS 0
#define VLYNQ2OCP_VLYNQ_CONTROL_RESET_NUMB 1
#define VLYNQ2OCP_VLYNQ_CONTROL_RESET_RES_VAL 0x0
//R/W
//VLYNQ2OCP_VLYNQ_STATUS
//-------------------
#define VLYNQ2OCP_VLYNQ_STATUS REG32(VLYNQ2OCP_BASE_ADDR_ARM+VLYNQ2OCP_VLYNQ_STATUS_OFFSET)
#define VLYNQ2OCP_VLYNQ_STATUS_DEBUG_POS 29
#define VLYNQ2OCP_VLYNQ_STATUS_DEBUG_NUMB 3
#define VLYNQ2OCP_VLYNQ_STATUS_DEBUG_RES_VAL 0x0
//R
#define VLYNQ2OCP_VLYNQ_STATUS_RESERVED_0_POS 27
#define VLYNQ2OCP_VLYNQ_STATUS_RESERVED_0_NUMB 2
#define VLYNQ2OCP_VLYNQ_STATUS_RESERVED_0_RES_VAL 0x0
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