📄 securewatchdog.h
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//R/W
#define SECUREWATCHDOG_WCLR_32_PRE_POS 5
#define SECUREWATCHDOG_WCLR_32_PRE_NUMB 1
#define SECUREWATCHDOG_WCLR_32_PRE_RES_VAL 0x1
//R/W
#define SECUREWATCHDOG_WCLR_32_PTV_POS 2
#define SECUREWATCHDOG_WCLR_32_PTV_NUMB 3
#define SECUREWATCHDOG_WCLR_32_PTV_RES_VAL 0x1
//R/W
//R/W
//SECUREWATCHDOG_WCRR
//-------------------
#define SECUREWATCHDOG_WCRR_16_0 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WCRR_OFFSET*coeff16_arm+0)
#define SECUREWATCHDOG_WCRR_16_0_TIME_COUNTER_POS 0
#define SECUREWATCHDOG_WCRR_16_0_TIME_COUNTER_NUMB 32
#define SECUREWATCHDOG_WCRR_16_0_TIME_COUNTER_RES_VAL 0x00000000
//R/W
#define SECUREWATCHDOG_WCRR_16_2 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WCRR_OFFSET*coeff16_arm+2)
#define SECUREWATCHDOG_WCRR_16_2_TIME_COUNTER_POS 0
#define SECUREWATCHDOG_WCRR_16_2_TIME_COUNTER_NUMB 32
#define SECUREWATCHDOG_WCRR_16_2_TIME_COUNTER_RES_VAL 0x00000000
//R/W
#define SECUREWATCHDOG_WCRR_32 REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WCRR_OFFSET*coeff32_arm)
#define SECUREWATCHDOG_WCRR_32_TIME_COUNTER_POS 0
#define SECUREWATCHDOG_WCRR_32_TIME_COUNTER_NUMB 32
#define SECUREWATCHDOG_WCRR_32_TIME_COUNTER_RES_VAL 0x00000000
//R/W
//SECUREWATCHDOG_WLDR
//-------------------
#define SECUREWATCHDOG_WLDR_16_0 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WLDR_OFFSET*coeff16_arm+0)
#define SECUREWATCHDOG_WLDR_16_0_TIME_LOAD_POS 0
#define SECUREWATCHDOG_WLDR_16_0_TIME_LOAD_NUMB 32
#define SECUREWATCHDOG_WLDR_16_0_TIME_LOAD_RES_VAL 0x00001FFF
//R/W
#define SECUREWATCHDOG_WLDR_16_2 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WLDR_OFFSET*coeff16_arm+2)
#define SECUREWATCHDOG_WLDR_16_2_TIME_LOAD_POS 0
#define SECUREWATCHDOG_WLDR_16_2_TIME_LOAD_NUMB 32
#define SECUREWATCHDOG_WLDR_16_2_TIME_LOAD_RES_VAL 0x000098FF
//R/W
#define SECUREWATCHDOG_WLDR_32 REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WLDR_OFFSET*coeff32_arm)
#define SECUREWATCHDOG_WLDR_32_TIME_LOAD_POS 0
#define SECUREWATCHDOG_WLDR_32_TIME_LOAD_NUMB 32
#define SECUREWATCHDOG_WLDR_32_TIME_LOAD_RES_VAL 0x98FF1FFF
//R/W
//SECUREWATCHDOG_WTGR
//-------------------
#define SECUREWATCHDOG_WTGR_16_0 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WTGR_OFFSET*coeff16_arm+0)
#define SECUREWATCHDOG_WTGR_16_0_TTGR_VALUE_POS 0
#define SECUREWATCHDOG_WTGR_16_0_TTGR_VALUE_NUMB 32
#define SECUREWATCHDOG_WTGR_16_0_TTGR_VALUE_RES_VAL 0x00000000
//R/W
#define SECUREWATCHDOG_WTGR_16_2 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WTGR_OFFSET*coeff16_arm+2)
#define SECUREWATCHDOG_WTGR_16_2_TTGR_VALUE_POS 0
#define SECUREWATCHDOG_WTGR_16_2_TTGR_VALUE_NUMB 32
#define SECUREWATCHDOG_WTGR_16_2_TTGR_VALUE_RES_VAL 0x00000000
//R/W
#define SECUREWATCHDOG_WTGR_32 REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WTGR_OFFSET*coeff32_arm)
#define SECUREWATCHDOG_WTGR_32_TTGR_VALUE_POS 0
#define SECUREWATCHDOG_WTGR_32_TTGR_VALUE_NUMB 32
#define SECUREWATCHDOG_WTGR_32_TTGR_VALUE_RES_VAL 0x00000000
//R/W
//SECUREWATCHDOG_WWPS
//-------------------
#define SECUREWATCHDOG_WWPS_16_0 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WWPS_OFFSET*coeff16_arm+0)
//R
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WSPR_POS 4
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WSPR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WSPR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WTGR_POS 3
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WTGR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WTGR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WLDR_POS 2
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WLDR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WLDR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WCRR_POS 1
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WCRR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WCRR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WCLR_POS 0
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WCLR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_0_W_PEND_WCLR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_2 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WWPS_OFFSET*coeff16_arm+2)
//R
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WSPR_POS 4
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WSPR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WSPR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WTGR_POS 3
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WTGR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WTGR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WLDR_POS 2
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WLDR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WLDR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WCRR_POS 1
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WCRR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WCRR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WCLR_POS 0
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WCLR_NUMB 1
#define SECUREWATCHDOG_WWPS_16_2_W_PEND_WCLR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_32 REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WWPS_OFFSET*coeff32_arm)
//R
#define SECUREWATCHDOG_WWPS_32_W_PEND_WSPR_POS 4
#define SECUREWATCHDOG_WWPS_32_W_PEND_WSPR_NUMB 1
#define SECUREWATCHDOG_WWPS_32_W_PEND_WSPR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_32_W_PEND_WTGR_POS 3
#define SECUREWATCHDOG_WWPS_32_W_PEND_WTGR_NUMB 1
#define SECUREWATCHDOG_WWPS_32_W_PEND_WTGR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_32_W_PEND_WLDR_POS 2
#define SECUREWATCHDOG_WWPS_32_W_PEND_WLDR_NUMB 1
#define SECUREWATCHDOG_WWPS_32_W_PEND_WLDR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_32_W_PEND_WCRR_POS 1
#define SECUREWATCHDOG_WWPS_32_W_PEND_WCRR_NUMB 1
#define SECUREWATCHDOG_WWPS_32_W_PEND_WCRR_RES_VAL 0x0
//R
#define SECUREWATCHDOG_WWPS_32_W_PEND_WCLR_POS 0
#define SECUREWATCHDOG_WWPS_32_W_PEND_WCLR_NUMB 1
#define SECUREWATCHDOG_WWPS_32_W_PEND_WCLR_RES_VAL 0x0
//R
//SECUREWATCHDOG_WSPR
//-------------------
#define SECUREWATCHDOG_WSPR_16_0 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WSPR_OFFSET*coeff16_arm+0)
#define SECUREWATCHDOG_WSPR_16_0_WSPR_VALUE_POS 0
#define SECUREWATCHDOG_WSPR_16_0_WSPR_VALUE_NUMB 32
#define SECUREWATCHDOG_WSPR_16_0_WSPR_VALUE_RES_VAL 0x00000000
//R/W
#define SECUREWATCHDOG_WSPR_16_2 REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WSPR_OFFSET*coeff16_arm+2)
#define SECUREWATCHDOG_WSPR_16_2_WSPR_VALUE_POS 0
#define SECUREWATCHDOG_WSPR_16_2_WSPR_VALUE_NUMB 32
#define SECUREWATCHDOG_WSPR_16_2_WSPR_VALUE_RES_VAL 0x00000000
//R/W
#define SECUREWATCHDOG_WSPR_32 REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WSPR_OFFSET*coeff32_arm)
#define SECUREWATCHDOG_WSPR_32_WSPR_VALUE_POS 0
#define SECUREWATCHDOG_WSPR_32_WSPR_VALUE_NUMB 32
#define SECUREWATCHDOG_WSPR_32_WSPR_VALUE_RES_VAL 0x00000000
//R/W
#endif
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