securewatchdog.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :securewatchdog.h
//
//   Date of Module Modification:3/6/02
//   Date of Generation :5/21/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _SECUREWATCHDOG__H
#define _SECUREWATCHDOG__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define coeff8_arm   1
#define coeff16_arm  1
#define coeff32_arm  1

//-------------------

#define            SECUREWATCHDOG_WIDR_OFFSET                                                                          0x00
#define            SECUREWATCHDOG_WD_SYSCONFIG_OFFSET                                                                  0x10
#define            SECUREWATCHDOG_WD_SYSSTATUS_OFFSET                                                                  0x14
#define            SECUREWATCHDOG_WCLR_OFFSET                                                                          0x24
#define            SECUREWATCHDOG_WCRR_OFFSET                                                                          0x28
#define            SECUREWATCHDOG_WLDR_OFFSET                                                                          0x2C
#define            SECUREWATCHDOG_WTGR_OFFSET                                                                          0x30
#define            SECUREWATCHDOG_WWPS_OFFSET                                                                          0x34
#define            SECUREWATCHDOG_WSPR_OFFSET                                                                          0x48




//SECUREWATCHDOG_WIDR
//-------------------
#define            SECUREWATCHDOG_WIDR_16_0                                                                            REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WIDR_OFFSET*coeff16_arm+0)


//R

#define            SECUREWATCHDOG_WIDR_16_0_WD_REV_POS                                                                   0
#define            SECUREWATCHDOG_WIDR_16_0_WD_REV_NUMB                                                                  8
#define            SECUREWATCHDOG_WIDR_16_0_WD_REV_RES_VAL                                                               0x10
//R

#define            SECUREWATCHDOG_WIDR_16_2                                                                            REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WIDR_OFFSET*coeff16_arm+2)


//R

#define            SECUREWATCHDOG_WIDR_16_2_WD_REV_POS                                                                   0
#define            SECUREWATCHDOG_WIDR_16_2_WD_REV_NUMB                                                                  8
#define            SECUREWATCHDOG_WIDR_16_2_WD_REV_RES_VAL                                                               0x10
//R

#define            SECUREWATCHDOG_WIDR_32                                                                              REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WIDR_OFFSET*coeff32_arm)


//R

#define            SECUREWATCHDOG_WIDR_32_WD_REV_POS                                                                     0
#define            SECUREWATCHDOG_WIDR_32_WD_REV_NUMB                                                                    8
#define            SECUREWATCHDOG_WIDR_32_WD_REV_RES_VAL                                                                 0x10
//R


//SECUREWATCHDOG_WD_SYSCONFIG
//-------------------
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0                                                                    REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WD_SYSCONFIG_OFFSET*coeff16_arm+0)


//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_EMUFREE_POS                                                          5
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_EMUFREE_NUMB                                                         1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_EMUFREE_RES_VAL                                                      0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_SOFTRESET_POS                                                        1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_SOFTRESET_NUMB                                                       1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_SOFTRESET_RES_VAL                                                    0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_AUTOIDLE_POS                                                         0
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_AUTOIDLE_NUMB                                                        1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_0_AUTOIDLE_RES_VAL                                                     0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2                                                                    REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WD_SYSCONFIG_OFFSET*coeff16_arm+2)


//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_EMUFREE_POS                                                          5
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_EMUFREE_NUMB                                                         1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_EMUFREE_RES_VAL                                                      0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_SOFTRESET_POS                                                        1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_SOFTRESET_NUMB                                                       1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_SOFTRESET_RES_VAL                                                    0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_AUTOIDLE_POS                                                         0
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_AUTOIDLE_NUMB                                                        1
#define            SECUREWATCHDOG_WD_SYSCONFIG_16_2_AUTOIDLE_RES_VAL                                                     0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_32                                                                      REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WD_SYSCONFIG_OFFSET*coeff32_arm)


//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_32_EMUFREE_POS                                                            5
#define            SECUREWATCHDOG_WD_SYSCONFIG_32_EMUFREE_NUMB                                                           1
#define            SECUREWATCHDOG_WD_SYSCONFIG_32_EMUFREE_RES_VAL                                                        0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_32_SOFTRESET_POS                                                          1
#define            SECUREWATCHDOG_WD_SYSCONFIG_32_SOFTRESET_NUMB                                                         1
#define            SECUREWATCHDOG_WD_SYSCONFIG_32_SOFTRESET_RES_VAL                                                      0x0
//R/W

#define            SECUREWATCHDOG_WD_SYSCONFIG_32_AUTOIDLE_POS                                                           0
#define            SECUREWATCHDOG_WD_SYSCONFIG_32_AUTOIDLE_NUMB                                                          1
#define            SECUREWATCHDOG_WD_SYSCONFIG_32_AUTOIDLE_RES_VAL                                                       0x0
//R/W


//SECUREWATCHDOG_WD_SYSSTATUS
//-------------------
#define            SECUREWATCHDOG_WD_SYSSTATUS_16_0                                                                    REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WD_SYSSTATUS_OFFSET*coeff16_arm+0)


//R

//R

#define            SECUREWATCHDOG_WD_SYSSTATUS_16_0_RESETDONE_POS                                                        0
#define            SECUREWATCHDOG_WD_SYSSTATUS_16_0_RESETDONE_NUMB                                                       1
#define            SECUREWATCHDOG_WD_SYSSTATUS_16_0_RESETDONE_RES_VAL                                                    0x1
//R

#define            SECUREWATCHDOG_WD_SYSSTATUS_16_2                                                                    REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WD_SYSSTATUS_OFFSET*coeff16_arm+2)


//R

//R

#define            SECUREWATCHDOG_WD_SYSSTATUS_16_2_RESETDONE_POS                                                        0
#define            SECUREWATCHDOG_WD_SYSSTATUS_16_2_RESETDONE_NUMB                                                       1
#define            SECUREWATCHDOG_WD_SYSSTATUS_16_2_RESETDONE_RES_VAL                                                    0x1
//R

#define            SECUREWATCHDOG_WD_SYSSTATUS_32                                                                      REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WD_SYSSTATUS_OFFSET*coeff32_arm)


//R

//R

#define            SECUREWATCHDOG_WD_SYSSTATUS_32_RESETDONE_POS                                                          0
#define            SECUREWATCHDOG_WD_SYSSTATUS_32_RESETDONE_NUMB                                                         1
#define            SECUREWATCHDOG_WD_SYSSTATUS_32_RESETDONE_RES_VAL                                                      0x1
//R


//SECUREWATCHDOG_WCLR
//-------------------
#define            SECUREWATCHDOG_WCLR_16_0                                                                            REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WCLR_OFFSET*coeff16_arm+0)


//R/W

#define            SECUREWATCHDOG_WCLR_16_0_PRE_POS                                                                      5
#define            SECUREWATCHDOG_WCLR_16_0_PRE_NUMB                                                                     1
#define            SECUREWATCHDOG_WCLR_16_0_PRE_RES_VAL                                                                  0x1
//R/W

#define            SECUREWATCHDOG_WCLR_16_0_PTV_POS                                                                      2
#define            SECUREWATCHDOG_WCLR_16_0_PTV_NUMB                                                                     3
#define            SECUREWATCHDOG_WCLR_16_0_PTV_RES_VAL                                                                  0x1
//R/W

//R/W

#define            SECUREWATCHDOG_WCLR_16_2                                                                            REG16(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WCLR_OFFSET*coeff16_arm+2)


//R/W

#define            SECUREWATCHDOG_WCLR_16_2_PRE_POS                                                                      5
#define            SECUREWATCHDOG_WCLR_16_2_PRE_NUMB                                                                     1
#define            SECUREWATCHDOG_WCLR_16_2_PRE_RES_VAL                                                                  0x1
//R/W

#define            SECUREWATCHDOG_WCLR_16_2_PTV_POS                                                                      2
#define            SECUREWATCHDOG_WCLR_16_2_PTV_NUMB                                                                     3
#define            SECUREWATCHDOG_WCLR_16_2_PTV_RES_VAL                                                                  0x1
//R/W

//R/W

#define            SECUREWATCHDOG_WCLR_32                                                                              REG32(SECUREWATCHDOG_BASE_ADDR_ARM+SECUREWATCHDOG_WCLR_OFFSET*coeff32_arm)