📄 mif.h
字号:
/*
===============================================================================
TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
Property of Texas Instruments
For Unrestricted Internal Use Only
Unauthorized reproduction and/or distribution is strictly prohibited.
This product is protected under copyright law and trade secret law
as an unpublished work.
Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
Filename : MIF.h
Description : Header file for the memory interface module
Project : Satustar
Author : Francois Reygagne freygagn@tif.ti.com
FUNCTIONS PROVIDED :
MIF_CheckResetEmifPriority
MIF_CheckResetImifPriority
MIF_CheckResetSlowIFConfigReg
MIF_CheckResetSlowCSConfigReg
MIF_CheckResetFastInterfaceSdramConfigReg
MIF_CheckResetFastInterfaceSdramMrsReg
MIF_SetEmifPriority: Set EMIF priority register to give consecutive access
either to Slow or fast EMIF Interface according to BusId value
MIF_SetImifPriority: Set IMIF priority register to give consecutive access
MIF_SetEmifPriority
MIF_SetFlashClockDivider
MIF_SetRetimedSwitch
MIF_SetReadWaitState
MIF_SetWriteWaitState
MIF_SetPgwstWelen
MIF_SetReadMode
MIF_SetBusMemoryWidth
MIF_InitFastInterfaceSdramConfigReg
MIF_InitFastInterfaceSdramMrsReg
MIF_EnableDSPEndianismTranslation
ASSEMBLER EXTERNAL FUNCTIONS
w_8_16_32: Test of memory access by byte, half word and word
multiple : Test of multiple read/write from/to memory
swap : Swap two memory addresses
test atomic write/read which must not be interrupted by DSP
str_ldr : fast store/load back to/from memory
===============================================================================
*/
#ifndef _MIF__HH
#define _MIF__HH
#include "top.h"
#include "flashintel.h"
//-----------------------------------------------------------------
//-- REGISTERS MAPPING ADDRESS -
//-----------------------------------------------------------------
//-- INTERNAL MEMORY INTERFACE PRIORITY REGISTER
#define MIF_PRIORITY_IMIF_REG_OFFSET 0x00
#define MIF_PRIORITY_IMIF_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_PRIORITY_IMIF_REG_OFFSET)
#define MIF_PRIORITY_IMIF_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_PRIORITY_IMIF_REG_OFFSET)
#define MIF_PRIORITY_IMIF_RESET_VALUE 0x00000000
#define MIF_PRIORITY_IMIF_MASK 0x0000FF77
//-- EXTERNAL MEMORY INTERFACE PRIORITY REGISTER
#define MIF_PRIORITY_EMIF_REG0_OFFSET 0x04
#define MIF_PRIORITY_EMIF_REG0_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_PRIORITY_EMIF_REG0_OFFSET)
#define MIF_PRIORITY_EMIF_REG0_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_PRIORITY_EMIF_REG0_OFFSET)
#define MIF_PRIORITY_EMIF_REG0_RESET_VALUE 0x00000000
#define MIF_PRIORITY_EMIF_REG0_MASK 0x0000FF77
#define MIF_PRIORITY_EMIF_REG1_OFFSET 0x08
#define MIF_PRIORITY_EMIF_REG1_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_PRIORITY_EMIF_REG1_OFFSET)
#define MIF_PRIORITY_EMIF_REG1_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_PRIORITY_EMIF_REG1_OFFSET)
#define MIF_PRIORITY_EMIF_REG1_RESET_VALUE 0x00000000
#define MIF_PRIORITY_EMIF_REG1_MASK 0x0000FF77
#define MIF_PRIORITY_EMIF_RESET_VALUE 0x00000000
//-----------------------------------------------------------------
//-- REGISTERS MAPPING ADDRESS -
//-----------------------------------------------------------------
//-- MIF Configuration Register
#define MIF_CONFIG_REG_OFFSET 0x0C
#define MIF_CONFIG_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_CONFIG_REG_OFFSET)
#define MIF_CONFIG_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_CONFIG_REG_OFFSET)
#define MIF_CONFIG_REG_RESET_VALUE 0x00000010
#define MIF_CONFIG_REG_MASK 0x0000001B
// bit definition of the register
#define MIF_CONFREG_RDY_MASK 0x00000010
#define MIF_CONFREG_PDE_MASK 0x00000008
#define MIF_CONFREG_PWD_EN_MASK 0x00000004
#define MIF_CONFREG_BM_MASK 0x00000002
#define MIF_CONFREG_WP_MASK 0x00000001
#define FLASH_READY TRUE
#define FLASH_NOT_READY FALSE
#define FLASH_ON_CS0 TRUE
#define FLASH_ON_CS3 FALSE
#define POWER_DOWN TRUE
#define NOT_POWER_DOWN FALSE
#define SWITCH_ON TRUE
#define SWITCH_OFF FALSE
#define WRITE_FORBIDEN TRUE
#define WRITE_AUTHORIZED FALSE
// 4 EMIF Slow Chip_Select Configuration Register (nCS0.. nCS3)
#define MIF_nCS0_CONFIG_REG_OFFSET 0x10
#define MIF_nCS0_CONFIG_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_nCS0_CONFIG_REG_OFFSET)
#define MIF_nCS0_CONFIG_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_nCS0_CONFIG_REG_OFFSET)
#define MIF_nCS1_CONFIG_REG_OFFSET 0x14
#define MIF_nCS1_CONFIG_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_nCS1_CONFIG_REG_OFFSET)
#define MIF_nCS1_CONFIG_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_nCS1_CONFIG_REG_OFFSET)
#define MIF_nCS2_CONFIG_REG_OFFSET 0x18
#define MIF_nCS2_CONFIG_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_nCS2_CONFIG_REG_OFFSET)
#define MIF_nCS2_CONFIG_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_nCS2_CONFIG_REG_OFFSET)
#define MIF_nCS3_CONFIG_REG_OFFSET 0x1C
#define MIF_nCS3_CONFIG_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_nCS3_CONFIG_REG_OFFSET)
#define MIF_nCS3_CONFIG_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_nCS3_CONFIG_REG_OFFSET)
#define MIF_nCSX_CONFIG_REG_RESET_VALUE_16 0x0000FFFB
#define MIF_nCSX_CONFIG_REG_RESET_VALUE_32 0x0010FFFB
#define MIF_nCSX_CONFIG_REG_MASK 0x0037FFFF
// Fast EMIF Chip_Select Configuration Register nCS4
#define MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_OFFSET 0x20
#define MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_OFFSET)
#define MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_OFFSET)
#define MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_RESET_VALUE 0x00618800
#define MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_MASK 0x0FFFFFFD
#define MIF_FAST_INTERFACE_SDRAM_MRS_REG_OFFSET 0x24
#define MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_SUP (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_FAST_INTERFACE_SDRAM_MRS_REG_OFFSET)
#define MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_USR (MEM_MEMORY_INTERFACE_USER_ADDR + MIF_FAST_INTERFACE_SDRAM_MRS_REG_OFFSET)
#define MIF_FAST_INTERFACE_SDRAM_MRS_RESET_VALUE 0x00000037
#define MIF_FAST_INTERFACE_SDRAM_MRS_MASK 0x0000027F
// DSP, DMA, LCD, LB and HSAB Timeout Configuration Register for Dynamic Priority
#define MIF_TIMEOUT1_CONFIG_REG_OFFSET 0x28
#define MIF_TIMEOUT1_CONFIG_REG_ADDR (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_TIMEOUT1_CONFIG_REG_OFFSET)
#define MIF_TIMEOUT2_CONFIG_REG_OFFSET 0x2C
#define MIF_TIMEOUT2_CONFIG_REG_ADDR (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_TIMEOUT2_CONFIG_REG_OFFSET)
#define MIF_TIMEOUT3_CONFIG_REG_OFFSET 0x30
#define MIF_TIMEOUT3_CONFIG_REG_ADDR (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_TIMEOUT3_CONFIG_REG_OFFSET)
//#define MIF_TIMEOUT3_CONFIG_REG_MASK 0x00FF00FF
#define MIF_TIMEOUT3_CONFIG_REG_MASK 0x000000FF
#define MIF_TIMEOUT_CONFIG_REG_RESET_VALUE 0x00000000
// DSP Endianism Translation Configuration Register
#define MIF_ENDIANISM_CONFIG_REG_OFFSET 0x34
#define MIF_ENDIANISM_CONFIG_REG_ADDR (MEM_MEMORY_INTERFACE_SUPERVISOR_ADDR + MIF_ENDIANISM_CONFIG_REG_OFFSET)
#define MIF_ENDIANISM_CONFIG_REG_MASK 0x00000001
#define MIF_ENDIANISM_CONFIG_REG_RESET_VALUE 0x00000000
// bit definition of the register
#define MIF_ENDIANISM_EN_MASK 0x00000001
#define MIF_ENDIANISM_BS_EN_MASK 0x00000002
//------------------------------------------------------------
// EMIF PRIORITY REGISTER
//-------------------------------------------------------------
#define MIF_ARM_PRIORITY_MSK 0x00000007 /* ARM Consecutive Access Mask */
#define MIF_DSP_PRIORITY_MSK 0x00000070 /* DSP Consecutive Access Mask */
#define MIF_DMA_PRIORITY_MSK 0x00000F00 /* DMA Consecutive Access Mask */
#define MIF_HOST_PRIORITY_MSK 0x0000F000 /* Host Consecutive Access Mask */
#define MIF_ARM_PRIORITY_BITPOS 0
#define MIF_DSP_PRIORITY_BITPOS 4
#define MIF_DMA_PRIORITY_BITPOS 8
#define MIF_HOST_PRIORITY_BITPOS 12
//---------------------------------------------------
// EMIF SLOW CHIP SELECT CONFIGURATION REGISTER -
//---------------------------------------------------
#define MIF_SLOW_CS_CONFIG_REG_RESET_VALUE 0x0010FFFB
//---------------------------------------------------
// EMIF SLOW INTERFACE CONFIGURATION REGISTER -
//---------------------------------------------------
#define MIF_FCLKDIV_MSK 0x00000003 /* Flash Clock Divider Mask */
#define MIF_RT_MSK 0x00000004 /* Re-timing control mask */
#define MIF_PNF_MSK 0x00000008 /* Pipeline/flow Through mask */
#define MIF_RDWST_MSK 0x000000F0 /* read wait state mask for async read */
#define MIF_WRWST_MSK 0x00000F00 /* write wait state mask */
#define MIF_PGWST_WELEN_MSK 0x0000F000 /* we pulse duration mask */
#define MIF_RDMODE_MSK 0x00070000 /* read mode mask */
#define MIF_BW_MSK 0x00100000 /* bus memory width mask */
#define MIF_FINTEL_MSK 0x00200000 /* flash intel mask */
#define MIF_FCLKDIV_BITPOS 0 /* Flash Clock Divider bit position */
#define MIF_RT_BITPOS 2 /* Re-timing control bit position */
#define MIF_PNF_BITPOS 3 /* Pipeline/flow Through bit position */
#define MIF_RDWST_BITPOS 4 /* read wait state bit position for async read */
#define MIF_WRWST_BITPOS 8 /* write wait state bit position */
#define MIF_PGWST_WELEN_BITPOS 12 /* we pulse duration bit position */
#define MIF_RDMODE_BITPOS 16 /* read mode bit position */
#define MIF_BW_BITPOS 20 /* bus memory width bit position */
#define MIF_FINTEL_BITPOS 21 /* bus memory width bit position */
//-------------------------------------------------------------
// EMIF FAST INTERFACE SDRAM CONFIGURATION REGISTER -
//-------------------------------------------------------------
#define MIF_FAST_IF_SDRAM_CONFIG_REG_RESET_VALUE 0x00618800
#define MIF_SELF_REFRESH_ENABLE_MSK 0x00000001
#define MIF_RETIMING_MSK 0x00000002
#define MIF_AUTO_REFRESH_MODE_MSK 0x0000000C
#define MIF_SDRAM_TYPE_MSK 0x000000F0
#define MIF_AUTO_REFRESH_COUNTER_MSK 0x00FFFF00
#define MIF_SDRAM_FREQUENCY_MSK 0x03000000
#define MIF_POWER_DOWN_ENABLE_MSK 0x04000000
#define MIF_CLOCK_SDRAM_DISABLEMSK 0x08000000
#define MIF_RETIMING_BITPOS 1
#define MIF_AUTO_REFRESH_MODE_BITPOS 2
#define MIF_SDRAM_TYPE_BITPOS 4
#define MIF_AUTO_REFRESH_COUNTER_BITPOS 8
#define MIF_SDRAM_FREQUENCY_BITPOS 24
#define MIF_POWER_DOWN_ENABLE_BITPOS 26
#define MIF_CLOCK_SDRAM_DISABLEBITPOS 27
//----------------------------------------------------------
// EMIF FAST INTERFACE SDRAM MRS REGISTER -
//----------------------------------------------------------
#define MIF_FAST_IF_SDRAM_MRS_REG_RESET_VALUE 0x00000037
#define MIF_PAGE_BURST_LENGTH_MSK 0x00000007
#define MIF_SERIAL_MSK 0x00000008
#define MIF_CAS_LATENCY_MSK 0x00000070
#define MIF_WRITE_BURST_MSK 0x00000200
#define MIF_SERIAL_BITPOS 3
#define MIF_CAS_LATENCY_BITPOS 4
#define MIF_WRITE_BURST_BITPOS 9
// Total Number of Slow Chip Select
#define MIF_SLOW_CHIP_SELECT_NUMBER 4
typedef UWORD32 REgAddrSlowCS_t [ MIF_SLOW_CHIP_SELECT_NUMBER ] ;
//-------------------------------------------------
//-- MIF_Slow_CS_Enum_t -
//-------------------------------------------------
typedef enum
{ MIF_Slow_nCS0 = 0,
MIF_Slow_nCS1 = 1,
MIF_Slow_nCS2 = 2,
MIF_Slow_nCS3 = 3 } MIF_Slow_CS_Enum_t;
//------------------------------------------------------------------------
//-- CONSTANTS TO PROGRAM THE EMIF SLOW REGISTER CS -
//------------------------------------------------------------------------
typedef enum { MIF_DIVIDE_BY_1 = 0, MIF_DIVIDE_BY_2 = 1,
MIF_DIVIDE_BY_4 = 2, MIF_DIVIDE_BY_6 = 3 } FCLKDIV_t;
typedef enum { MIF_NOT_RETIMED = 0, MIF_RETIMED = 1 } RetimingControl_t;
typedef enum { NO_FLASH_INTEL = 0, FLASH_INTEL = 1 } Package_t;
typedef enum { MIF_ASYNC_READ = 0,
MIF_PAGE_ROM_READ_WORDS4 = 1,
MIF_PAGE_ROM_READ_WORDS8 = 2,
MIF_PAGE_ROM_READ_WORDS16 = 3,
MIF_SYNC_BURST_READ_TI = 4,
MIF_SYNC_BURST_READ_SMART3= 5,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -