macro_set.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;-------------------------------------------------------------------
;--                                                               --
;--              File: macro_set.asm		                  --
;--              Author: Wei Jiang				  --                                              
;--              Content: macros used in MMU tests                --
;--              Language: TMS470R1x Assembly (ARM)               --
;--                                                               --
;-------------------------------------------------------------------
setmem1	.macro adrD1,valD1
	
	LDR	R1, adrD1
	LDR	R2, valD1		
	STR	R2, [R1]      	;-- set the 1st level descriptor
	
	.endm
;------------------------------------------------------------------
setmem2	.macro adrD1,valD1,adrD2,valD2
	
	LDR	R1, adrD1
	LDR	R2, valD1		
	STR	R2, [R1]      ;-- set the 1st level descriptor

	LDR	R1, adrD2
	LDR	R2, valD2	
	STR	R2, [R1]      ;-- set the 2nd level descriptor
	
	.endm
;------------------------------------------------------------------
setspfine .macro addL1,L1,start_addL2,L2
	LDR	R1, addL1
	LDR	R2, L1
	STR	R2, [R1]		;-- set L1 for small page fine table
	
	LDR	R1, start_addL2
	LDR	R2, L2
	MOV	R0, #4
	MOV	R3, #0
loop1	STR	R2, [R1]
	ADD	R1, R1, #4
	ADD 	R3, R3, #1
	CMP	R3, R0
	BNE	loop1			;-- set L2 for in 4 consective address
					;-- start from start_addL2
	.endm
;------------------------------------------------------------------
setlpcoarse .macro addL1,L1,start_addL2,L2
	LDR	R1, addL1
	LDR	R2, L1
	STR	R2, [R1]		;-- set L1 for small page fine table
	
	LDR	R1, start_addL2
	LDR	R2, L2
	MOV	R0, #16
	MOV	R3, #0
loop2	STR	R2, [R1]
	ADD	R1, R1, #4
	ADD 	R3, R3, #1
	CMP	R3, R0
	BNE	loop2			;-- set L2 for in 16 consective address
					;-- start from start_addL2
	.endm
;------------------------------------------------------------------
setlpfine .macro addL1,L1,start_addL2,L2
	LDR	R1, addL1
	LDR	R2, L1
	STR	R2, [R1]		;-- set L1 for small page fine table
	
	LDR	R1, start_addL2
	LDR	R2, L2
	MOV	R0, #64
	MOV	R3, #0
loop3	STR	R2, [R1]
	ADD	R1, R1, #4
	ADD 	R3, R3, #1
	CMP	R3, R0
	BNE	loop3			;-- set L2 for in 64 consective address
					;-- start from start_addL2
	.endm
;------------------------------------------------------------------	
setbase	.macro tbase
	
	LDR	R2, tbase
	NOP 				;-- POTENTIAL BUG THIS NOP NEED TO BE REMOVED
        MCR	p15,#0,R2,c2,c0 ;-- set the translation table base reg.
	
	.endm
;------------------------------------------------------------------	
setdom	.macro valR3

	LDR	R3, valR3
	NOP                             ;-- POTENTIAL BUG THIS NOP NEED TO BE REMOVED
	MCR	p15,#0,R3,c3,c0	;-- set up the domains
	
	.endm
;------------------------------------------------------------------