omap_32_armt3.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :omap_32_armt3.h
//
//   Date of Module Modification:4/25/02
//   Date of Generation :5/3/02
//
//
//========================================================================
#include "omap_32_mapping.h"
#ifndef _ARMT3__H
#define _ARMT3__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            ARMT3_CNTL_TIMER_OFFSET                                                                             0x00
#define            ARMT3_LOAD_TIM_OFFSET                                                                               0x04
#define            ARMT3_READ_TIM_OFFSET                                                                               0x08




//ARMT3_CNTL_TIMER
//-------------------
#define            ARMT3_CNTL_TIMER                                                                                    REG32(ARMT3_BASE_ADDR_ARM+ARMT3_CNTL_TIMER_OFFSET)


//R/W

#define            ARMT3_CNTL_TIMER_FREE_POS                                                                             6
#define            ARMT3_CNTL_TIMER_FREE_NUMB                                                                            1
#define            ARMT3_CNTL_TIMER_FREE_RES_VAL                                                                         0x0
//R/W

#define            ARMT3_CNTL_TIMER_CLOCK_ENABLE_POS                                                                     5
#define            ARMT3_CNTL_TIMER_CLOCK_ENABLE_NUMB                                                                    1
#define            ARMT3_CNTL_TIMER_CLOCK_ENABLE_RES_VAL                                                                 0x0
//R/W

#define            ARMT3_CNTL_TIMER_PTV_POS                                                                              2
#define            ARMT3_CNTL_TIMER_PTV_NUMB                                                                             3
#define            ARMT3_CNTL_TIMER_PTV_RES_VAL                                                                          0x0
//R/W

#define            ARMT3_CNTL_TIMER_AR_POS                                                                               1
#define            ARMT3_CNTL_TIMER_AR_NUMB                                                                              1
#define            ARMT3_CNTL_TIMER_AR_RES_VAL                                                                           0x0
//R/W

#define            ARMT3_CNTL_TIMER_ST_POS                                                                               0
#define            ARMT3_CNTL_TIMER_ST_NUMB                                                                              1
#define            ARMT3_CNTL_TIMER_ST_RES_VAL                                                                           0x0
//R/W


//ARMT3_LOAD_TIM
//-------------------
#define            ARMT3_LOAD_TIM                                                                                      REG32(ARMT3_BASE_ADDR_ARM+ARMT3_LOAD_TIM_OFFSET)


#define            ARMT3_LOAD_TIM_LOAD_TIM_POS                                                                           0
#define            ARMT3_LOAD_TIM_LOAD_TIM_NUMB                                                                          32
#define            ARMT3_LOAD_TIM_LOAD_TIM_RES_VAL                                                                       0x0
//W


//ARMT3_READ_TIM
//-------------------
#define            ARMT3_READ_TIM                                                                                      REG32(ARMT3_BASE_ADDR_ARM+ARMT3_READ_TIM_OFFSET)


#define            ARMT3_READ_TIM_READ_TIM_POS                                                                           0
#define            ARMT3_READ_TIM_READ_TIM_NUMB                                                                          32
#define            ARMT3_READ_TIM_READ_TIM_RES_VAL                                                                       0x0
//R

#endif