📄 rtc.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :rtc.h
//
// Date of Module Modification:7/22/02
// Date of Generation :8/29/02
//
//
//========================================================================
#ifndef _RTC__H
#define _RTC__H
#include "mapping.h"
#include "global_types.h"
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define coeff8_arm 1
#define coeff16_arm 1
#define coeff32_arm 1
//-------------------
#define RTC_SECONDS_REG_OFFSET 0x00
#define RTC_MINUTES_REG_OFFSET 0x04
#define RTC_HOURS_REG_OFFSET 0x08
#define RTC_DAYS_REG_OFFSET 0x0C
#define RTC_MONTHS_REG_OFFSET 0x10
#define RTC_YEARS_REG_OFFSET 0x14
#define RTC_WEEK_REG_OFFSET 0x18
#define RTC_ALARM_SECONDS_REG_OFFSET 0x20
#define RTC_ALARM_MINUTES_REG_OFFSET 0x24
#define RTC_ALARM_HOURS_REG_OFFSET 0x28
#define RTC_ALARM_DAYS_REG_OFFSET 0x2C
#define RTC_ALARM_MONTHS_REG_OFFSET 0x30
#define RTC_ALARM_YEARS_REG_OFFSET 0x34
#define RTC_RTC_CTRL_REGISTER_OFFSET 0x40
#define RTC_RTC_STATUS_REG_OFFSET 0x44
#define RTC_RTC_INTERRUPTS_REG_OFFSET 0x48
#define RTC_RTC_COMP_LSB_REG_OFFSET 0x4C
#define RTC_RTC_COMP_MSB_REG_OFFSET 0x50
#define RTC_RTC_OSC_REG_OFFSET 0x54
//RTC_SECONDS_REG
//-------------------
#define RTC_SECONDS_REG_8_0 REG8(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff8_arm+0)
#define RTC_SECONDS_REG_8_0_SEC1_POS 4
#define RTC_SECONDS_REG_8_0_SEC1_NUMB 4
#define RTC_SECONDS_REG_8_0_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_0_SEC0_POS 0
#define RTC_SECONDS_REG_8_0_SEC0_NUMB 4
#define RTC_SECONDS_REG_8_0_SEC0_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_1 REG8(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff8_arm+1)
#define RTC_SECONDS_REG_8_1_SEC1_POS 4
#define RTC_SECONDS_REG_8_1_SEC1_NUMB 4
#define RTC_SECONDS_REG_8_1_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_1_SEC0_POS 0
#define RTC_SECONDS_REG_8_1_SEC0_NUMB 4
#define RTC_SECONDS_REG_8_1_SEC0_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_2 REG8(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff8_arm+2)
#define RTC_SECONDS_REG_8_2_SEC1_POS 4
#define RTC_SECONDS_REG_8_2_SEC1_NUMB 4
#define RTC_SECONDS_REG_8_2_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_2_SEC0_POS 0
#define RTC_SECONDS_REG_8_2_SEC0_NUMB 4
#define RTC_SECONDS_REG_8_2_SEC0_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_3 REG8(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff8_arm+3)
#define RTC_SECONDS_REG_8_3_SEC1_POS 4
#define RTC_SECONDS_REG_8_3_SEC1_NUMB 4
#define RTC_SECONDS_REG_8_3_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_8_3_SEC0_POS 0
#define RTC_SECONDS_REG_8_3_SEC0_NUMB 4
#define RTC_SECONDS_REG_8_3_SEC0_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_16_0 REG16(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff16_arm+0)
#define RTC_SECONDS_REG_16_0_SEC1_POS 4
#define RTC_SECONDS_REG_16_0_SEC1_NUMB 4
#define RTC_SECONDS_REG_16_0_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_16_0_SEC0_POS 0
#define RTC_SECONDS_REG_16_0_SEC0_NUMB 4
#define RTC_SECONDS_REG_16_0_SEC0_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_16_2 REG16(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff16_arm+2)
#define RTC_SECONDS_REG_16_2_SEC1_POS 4
#define RTC_SECONDS_REG_16_2_SEC1_NUMB 4
#define RTC_SECONDS_REG_16_2_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_16_2_SEC0_POS 0
#define RTC_SECONDS_REG_16_2_SEC0_NUMB 4
#define RTC_SECONDS_REG_16_2_SEC0_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_32 REG32(RTC_BASE_ADDR_ARM+RTC_SECONDS_REG_OFFSET*coeff32_arm)
#define RTC_SECONDS_REG_32_SEC1_POS 4
#define RTC_SECONDS_REG_32_SEC1_NUMB 4
#define RTC_SECONDS_REG_32_SEC1_RES_VAL 0x0
//R/W
#define RTC_SECONDS_REG_32_SEC0_POS 0
#define RTC_SECONDS_REG_32_SEC0_NUMB 4
#define RTC_SECONDS_REG_32_SEC0_RES_VAL 0x0
//R/W
//RTC_MINUTES_REG
//-------------------
#define RTC_MINUTES_REG_8_0 REG8(RTC_BASE_ADDR_ARM+RTC_MINUTES_REG_OFFSET*coeff8_arm+0)
#define RTC_MINUTES_REG_8_0_MIN1_POS 4
#define RTC_MINUTES_REG_8_0_MIN1_NUMB 4
#define RTC_MINUTES_REG_8_0_MIN1_RES_VAL 0x0
//R/W
#define RTC_MINUTES_REG_8_0_MIN0_POS 0
#define RTC_MINUTES_REG_8_0_MIN0_NUMB 4
#define RTC_MINUTES_REG_8_0_MIN0_RES_VAL 0x0
//R/W
#define RTC_MINUTES_REG_8_1 REG8(RTC_BASE_ADDR_ARM+RTC_MINUTES_REG_OFFSET*coeff8_arm+1)
#define RTC_MINUTES_REG_8_1_MIN1_POS 4
#define RTC_MINUTES_REG_8_1_MIN1_NUMB 4
#define RTC_MINUTES_REG_8_1_MIN1_RES_VAL 0x0
//R/W
#define RTC_MINUTES_REG_8_1_MIN0_POS 0
#define RTC_MINUTES_REG_8_1_MIN0_NUMB 4
#define RTC_MINUTES_REG_8_1_MIN0_RES_VAL 0x0
//R/W
#define RTC_MINUTES_REG_8_2 REG8(RTC_BASE_ADDR_ARM+RTC_MINUTES_REG_OFFSET*coeff8_arm+2)
#define RTC_MINUTES_REG_8_2_MIN1_POS 4
#define RTC_MINUTES_REG_8_2_MIN1_NUMB 4
#define RTC_MINUTES_REG_8_2_MIN1_RES_VAL 0x0
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