omap_32_armrhea_priv.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_TIMEOUT_EN_NUMB                                                       1
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_TIMEOUT_EN_RES_VAL                                                    0x1
//R/W


//ARMRHEA_PRIV_ADDRESS_DBG
//-------------------
#define            ARMRHEA_PRIV_ADDRESS_DBG                                                                            REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_ADDRESS_DBG_OFFSET)


#define            ARMRHEA_PRIV_ADDRESS_DBG_ADDRESS_DBG_POS                                                              0
#define            ARMRHEA_PRIV_ADDRESS_DBG_ADDRESS_DBG_NUMB                                                             16
#define            ARMRHEA_PRIV_ADDRESS_DBG_ADDRESS_DBG_RES_VAL                                                          0xFFFF
//R


//ARMRHEA_PRIV_DATA_DEBUG_LOW
//-------------------
#define            ARMRHEA_PRIV_DATA_DEBUG_LOW                                                                         REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_DATA_DEBUG_LOW_OFFSET)


#define            ARMRHEA_PRIV_DATA_DEBUG_LOW_DATA_DBG_LOW_POS                                                          0
#define            ARMRHEA_PRIV_DATA_DEBUG_LOW_DATA_DBG_LOW_NUMB                                                         16
#define            ARMRHEA_PRIV_DATA_DEBUG_LOW_DATA_DBG_LOW_RES_VAL                                                      0xFFFF
//R


//ARMRHEA_PRIV_DATA_DEBUG_HIGH
//-------------------
#define            ARMRHEA_PRIV_DATA_DEBUG_HIGH                                                                        REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_DATA_DEBUG_HIGH_OFFSET)


#define            ARMRHEA_PRIV_DATA_DEBUG_HIGH_DATA_DBG_HIGH_POS                                                        0
#define            ARMRHEA_PRIV_DATA_DEBUG_HIGH_DATA_DBG_HIGH_NUMB                                                       16
#define            ARMRHEA_PRIV_DATA_DEBUG_HIGH_DATA_DBG_HIGH_RES_VAL                                                    0xFFFF
//R


//ARMRHEA_PRIV_DEBUG_CNTR_SIG
//-------------------
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG                                                                         REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_DEBUG_CNTR_SIG_OFFSET)


//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_DMA_DISABLE_POS                                                       12
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_DMA_DISABLE_NUMB                                                      1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_DMA_DISABLE_RES_VAL                                                   0x0
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_ABORT_FLAG_POS                                                            11
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_ABORT_FLAG_NUMB                                                           1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_ABORT_FLAG_RES_VAL                                                        0x0
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_HOST_ID_POS                                                               9
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_HOST_ID_NUMB                                                              2
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_HOST_ID_RES_VAL                                                           0x00
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_BURST_POS                                                             8
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_BURST_NUMB                                                            1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_BURST_RES_VAL                                                         0x0
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_PERHMAS_POS                                                           6
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_PERHMAS_NUMB                                                          2
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_PERHMAS_RES_VAL                                                       0x11
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_MAS_POS                                                               4
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_MAS_NUMB                                                              2
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_MAS_RES_VAL                                                           0x11
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_NSUPV_POS                                                             3
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_NSUPV_NUMB                                                            1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_NSUPV_RES_VAL                                                         0x1
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_RNW_POS                                                               2
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_RNW_NUMB                                                              1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_RNW_RES_VAL                                                           0x1
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_WR_SIZE_POS                                                           1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_WR_SIZE_NUMB                                                          1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_WR_SIZE_RES_VAL                                                       0x0
//R

#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_TIMEOUT_POS                                                           0
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_TIMEOUT_NUMB                                                          1
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_DBG_TIMEOUT_RES_VAL                                                       0x0
//R


//ARMRHEA_PRIV_ACCESS_CNTL
//-------------------
#define            ARMRHEA_PRIV_ACCESS_CNTL                                                                            REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_ACCESS_CNTL_OFFSET)


#define            ARMRHEA_PRIV_ACCESS_CNTL_DPS_EN_POS                                                                   3
#define            ARMRHEA_PRIV_ACCESS_CNTL_DPS_EN_NUMB                                                                  1
#define            ARMRHEA_PRIV_ACCESS_CNTL_DPS_EN_RES_VAL                                                               0x0
//R/W

#define            ARMRHEA_PRIV_ACCESS_CNTL_MASK_OCPI_NABORT_POS                                                         2
#define            ARMRHEA_PRIV_ACCESS_CNTL_MASK_OCPI_NABORT_NUMB                                                        1
#define            ARMRHEA_PRIV_ACCESS_CNTL_MASK_OCPI_NABORT_RES_VAL                                                     0x0
//R/W

#define            ARMRHEA_PRIV_ACCESS_CNTL_MASK_DMA_NABORT_POS                                                          1
#define            ARMRHEA_PRIV_ACCESS_CNTL_MASK_DMA_NABORT_NUMB                                                         1
#define            ARMRHEA_PRIV_ACCESS_CNTL_MASK_DMA_NABORT_RES_VAL                                                      0x0
//R/W

#define            ARMRHEA_PRIV_ACCESS_CNTL_DMA_ENABLE_POS                                                               0
#define            ARMRHEA_PRIV_ACCESS_CNTL_DMA_ENABLE_NUMB                                                              1
#define            ARMRHEA_PRIV_ACCESS_CNTL_DMA_ENABLE_RES_VAL                                                           0x1
//R/W

#endif