omap_32_armrhea_priv.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :omap_32_armrhea_priv.h
//
//   Date of Module Modification:5/2/02
//   Date of Generation :5/3/02
//
//
//========================================================================
#include "omap_32_mapping.h"
#ifndef _ARMRHEA_PRIV__H
#define _ARMRHEA_PRIV__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            ARMRHEA_PRIV_RHEA_CNTL_OFFSET                                                                       0x00
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_OFFSET                                                                  0x04
#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_OFFSET                                                                   0x08
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_OFFSET                                                              0x0C
#define            ARMRHEA_PRIV_ADDRESS_DBG_OFFSET                                                                     0x10
#define            ARMRHEA_PRIV_DATA_DEBUG_LOW_OFFSET                                                                  0x14
#define            ARMRHEA_PRIV_DATA_DEBUG_HIGH_OFFSET                                                                 0x18
#define            ARMRHEA_PRIV_DEBUG_CNTR_SIG_OFFSET                                                                  0x1C
#define            ARMRHEA_PRIV_ACCESS_CNTL_OFFSET                                                                     0x20




//ARMRHEA_PRIV_RHEA_CNTL
//-------------------
#define            ARMRHEA_PRIV_RHEA_CNTL                                                                              REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_RHEA_CNTL_OFFSET)


#define            ARMRHEA_PRIV_RHEA_CNTL_TIMEOUT_POS                                                                    8
#define            ARMRHEA_PRIV_RHEA_CNTL_TIMEOUT_NUMB                                                                   8
#define            ARMRHEA_PRIV_RHEA_CNTL_TIMEOUT_RES_VAL                                                                0xFF
//R/W

#define            ARMRHEA_PRIV_RHEA_CNTL_ACCESS_FACTOR1_POS                                                             4
#define            ARMRHEA_PRIV_RHEA_CNTL_ACCESS_FACTOR1_NUMB                                                            4
#define            ARMRHEA_PRIV_RHEA_CNTL_ACCESS_FACTOR1_RES_VAL                                                         0x1
//R/W

#define            ARMRHEA_PRIV_RHEA_CNTL_ACCESS_FACTOR0_POS                                                             0
#define            ARMRHEA_PRIV_RHEA_CNTL_ACCESS_FACTOR0_NUMB                                                            4
#define            ARMRHEA_PRIV_RHEA_CNTL_ACCESS_FACTOR0_RES_VAL                                                         0x1
//R/W


//ARMRHEA_PRIV_RHEA_BUS_ALLOC
//-------------------
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC                                                                         REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_RHEA_BUS_ALLOC_OFFSET)


//R

#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_EXTNINT_PRIORITY_POS                                                      5
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_EXTNINT_PRIORITY_NUMB                                                     1
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_EXTNINT_PRIORITY_RES_VAL                                                  0x0
//R/W

#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_FIXNROUND_PRIORITY_POS                                                    4
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_FIXNROUND_PRIORITY_NUMB                                                   1
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_FIXNROUND_PRIORITY_RES_VAL                                                0x0
//R/W

#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_PRIORITY_ENABLE_POS                                                       3
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_PRIORITY_ENABLE_NUMB                                                      1
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_PRIORITY_ENABLE_RES_VAL                                                   0x1
//R/W

#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_RHEA_PRIORITY_POS                                                         0
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_RHEA_PRIORITY_NUMB                                                        3
#define            ARMRHEA_PRIV_RHEA_BUS_ALLOC_RHEA_PRIORITY_RES_VAL                                                     0x1
//R/W


//ARMRHEA_PRIV_ARM_RHEA_CNTL
//-------------------
#define            ARMRHEA_PRIV_ARM_RHEA_CNTL                                                                          REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_ARM_RHEA_CNTL_OFFSET)


#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_W_BUF_EN_1_POS                                                             1
#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_W_BUF_EN_1_NUMB                                                            1
#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_W_BUF_EN_1_RES_VAL                                                         0x0
//R/W

#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_W_BUF_EN_0_POS                                                             0
#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_W_BUF_EN_0_NUMB                                                            1
#define            ARMRHEA_PRIV_ARM_RHEA_CNTL_W_BUF_EN_0_RES_VAL                                                         0x0
//R/W


//ARMRHEA_PRIV_ENHANCED_RHEA_CNTL
//-------------------
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL                                                                     REG16(ARMRHEA_PRIV_BASE_ADDR_ARM+ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_OFFSET)


//R/W

#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_MASK_ARM_NABORT_POS                                                   3
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_MASK_ARM_NABORT_NUMB                                                  1
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_MASK_ARM_NABORT_RES_VAL                                               0x1
//R/W

//R/W

#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_MASK_IT_POS                                                           1
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_MASK_IT_NUMB                                                          1
#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_MASK_IT_RES_VAL                                                       0x1
//R/W

#define            ARMRHEA_PRIV_ENHANCED_RHEA_CNTL_TIMEOUT_EN_POS                                                        0