ccp.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :ccp.h
//
//   Date of Module Modification:7/25/02
//   Date of Generation :5/15/02
//
//   Date of Module Modification:04/28/3 
//  CCP address offset rhea to ocp
//========================================================================
#include "mapping.h"
#ifndef _CCP__H
#define _CCP__H



#define CCP_FIFO_TRIGGER_LEVEL   4


/*************************************************************************
 *    Everything below this is auto-generated.  Modify with caution.
 */

//BEGIN INC GENERATION
//--------------------------------------

	
//Register Offset			      OCP  // Rhea    debug  // OCP
//-------------------
#define            CCP_IDR_OFFSET             0x00 // 0x00 //  0x00  // 0x00
#define            CCP_FSCR_OFFSET            0x10 // 0x04 //  0x01  // 0x10
#define            CCP_FECR_OFFSET            0x20 // 0x08 //  0x02  // 0x20
#define            CCP_LSCR_OFFSET            0x30 // 0x0C //  0x03  // 0x30
#define            CCP_LECR_OFFSET            0x40 // 0x10 //  0x04  // 0x40
#define            CCP_CR_OFFSET              0x50 // 0x14 //  0x05  // 0x50
#define            CCP_DFR_OFFSET             0x60 // 0x18 //  0x06  // 0x60
#define            CCP_FIFODATAR_OFFSET       0x70 // 0x1C //  0x07  // 0x70
#define            CCP_STATUSR_OFFSET         0x80 // 0x20 //  0x08  // 0x80
#define            CCP_STATUSMASKR_OFFSET     0x90 // 0x24 //  0x09  // 0x90
#define            CCP_BUSCLKENR_OFFSET       0xa0 // 0x28 //  0x10  // 0xa0




//CCP_IDR
//-------------------
#define            CCP_IDR                                                                                          REG32(CCP_BASE_ADDR_ARM+CCP_IDR_OFFSET)


#define            CCP_IDR_IDR_POS                                                                                    0
#define            CCP_IDR_IDR_NUMB                                                                                   32
#define            CCP_IDR_IDR_RES_VAL                                                                                0x00000000
//R/W


//CCP_FSCR
//-------------------
#define            CCP_FSCR                                                                                         REG32(CCP_BASE_ADDR_ARM+CCP_FSCR_OFFSET)


#define            CCP_FSCR_FSC_POS                                                                                   0
#define            CCP_FSCR_FSC_NUMB                                                                                  32
#define            CCP_FSCR_FSC_RES_VAL                                                                               0xFF000002
//R/W


//CCP_FECR
//-------------------
#define            CCP_FECR                                                                                         REG32(CCP_BASE_ADDR_ARM+CCP_FECR_OFFSET)


#define            CCP_FECR_FEC_POS                                                                                   0
#define            CCP_FECR_FEC_NUMB                                                                                  32
#define            CCP_FECR_FEC_RES_VAL                                                                               0xFF000003
//R/W


//CCP_LSCR
//-------------------
#define            CCP_LSCR                                                                                         REG32(CCP_BASE_ADDR_ARM+CCP_LSCR_OFFSET)


#define            CCP_LSCR_LSC_POS                                                                                   0
#define            CCP_LSCR_LSC_NUMB                                                                                  32
#define            CCP_LSCR_LSC_RES_VAL                                                                               0xFF000000
//R/W


//CCP_LECR
//-------------------
#define            CCP_LECR                                                                                         REG32(CCP_BASE_ADDR_ARM+CCP_LECR_OFFSET)


#define            CCP_LECR_LEC_POS                                                                                   0
#define            CCP_LECR_LEC_NUMB                                                                                  32
#define            CCP_LECR_LEC_RES_VAL                                                                               0xFF000001
//R/W


//CCP_CR
//-------------------
#define            CCP_CR                                                                                           REG32(CCP_BASE_ADDR_ARM+CCP_CR_OFFSET)


#define            CCP_CR_LINECOUNTENABLE_POS                                                                         10
#define            CCP_CR_LINECOUNTENABLE_NUMB                                                                        1
#define            CCP_CR_LINECOUNTENABLE_RES_VAL                                                                     0x0
//R/W

#define            CCP_CR_LINECOUNTERLIMIT_POS                                                                        0
#define            CCP_CR_LINECOUNTERLIMIT_NUMB                                                                       10
#define            CCP_CR_LINECOUNTERLIMIT_RES_VAL                                                                    0x3FF
//R/W


//CCP_DFR
//-------------------
#define            CCP_DFR                                                                                          REG32(CCP_BASE_ADDR_ARM+CCP_DFR_OFFSET)


#define            CCP_DFR_DATAFORMATSELECT_POS                                                                       1
#define            CCP_DFR_DATAFORMATSELECT_NUMB                                                                      2
#define            CCP_DFR_DATAFORMATSELECT_RES_VAL                                                                   0x0
//R/W

#define            CCP_DFR_CCPSOFTRESET_POS                                                                           0
#define            CCP_DFR_CCPSOFTRESET_NUMB                                                                          1
#define            CCP_DFR_CCPSOFTRESET_RES_VAL                                                                       0x1
//R/W


//CCP_FIFODATAR
//-------------------
#define            CCP_FIFODATAR                                                                                    REG32(CCP_BASE_ADDR_ARM+CCP_FIFODATAR_OFFSET)