spi.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//R/W

#define            SPI_IER_8_0_MSK2_POS                                                                                  2
#define            SPI_IER_8_0_MSK2_NUMB                                                                                 1
#define            SPI_IER_8_0_MSK2_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_0_MSK1_POS                                                                                  1
#define            SPI_IER_8_0_MSK1_NUMB                                                                                 1
#define            SPI_IER_8_0_MSK1_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_0_MSK0_POS                                                                                  0
#define            SPI_IER_8_0_MSK0_NUMB                                                                                 1
#define            SPI_IER_8_0_MSK0_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_1                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET*coeff8_arm+1)


#define            SPI_IER_8_1_RESERVED_POS                                                                              5
#define            SPI_IER_8_1_RESERVED_NUMB                                                                             27
#define            SPI_IER_8_1_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_IER_8_1_MSK4_POS                                                                                  4
#define            SPI_IER_8_1_MSK4_NUMB                                                                                 1
#define            SPI_IER_8_1_MSK4_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_1_MSK3_POS                                                                                  3
#define            SPI_IER_8_1_MSK3_NUMB                                                                                 1
#define            SPI_IER_8_1_MSK3_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_1_MSK2_POS                                                                                  2
#define            SPI_IER_8_1_MSK2_NUMB                                                                                 1
#define            SPI_IER_8_1_MSK2_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_1_MSK1_POS                                                                                  1
#define            SPI_IER_8_1_MSK1_NUMB                                                                                 1
#define            SPI_IER_8_1_MSK1_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_1_MSK0_POS                                                                                  0
#define            SPI_IER_8_1_MSK0_NUMB                                                                                 1
#define            SPI_IER_8_1_MSK0_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_2                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET*coeff8_arm+2)


#define            SPI_IER_8_2_RESERVED_POS                                                                              5
#define            SPI_IER_8_2_RESERVED_NUMB                                                                             27
#define            SPI_IER_8_2_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_IER_8_2_MSK4_POS                                                                                  4
#define            SPI_IER_8_2_MSK4_NUMB                                                                                 1
#define            SPI_IER_8_2_MSK4_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_2_MSK3_POS                                                                                  3
#define            SPI_IER_8_2_MSK3_NUMB                                                                                 1
#define            SPI_IER_8_2_MSK3_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_2_MSK2_POS                                                                                  2
#define            SPI_IER_8_2_MSK2_NUMB                                                                                 1
#define            SPI_IER_8_2_MSK2_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_2_MSK1_POS                                                                                  1
#define            SPI_IER_8_2_MSK1_NUMB                                                                                 1
#define            SPI_IER_8_2_MSK1_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_2_MSK0_POS                                                                                  0
#define            SPI_IER_8_2_MSK0_NUMB                                                                                 1
#define            SPI_IER_8_2_MSK0_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_3                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET*coeff8_arm+3)


#define            SPI_IER_8_3_RESERVED_POS                                                                              5
#define            SPI_IER_8_3_RESERVED_NUMB                                                                             27
#define            SPI_IER_8_3_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_IER_8_3_MSK4_POS                                                                                  4
#define            SPI_IER_8_3_MSK4_NUMB                                                                                 1
#define            SPI_IER_8_3_MSK4_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_3_MSK3_POS                                                                                  3
#define            SPI_IER_8_3_MSK3_NUMB                                                                                 1
#define            SPI_IER_8_3_MSK3_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_3_MSK2_POS                                                                                  2
#define            SPI_IER_8_3_MSK2_NUMB                                                                                 1
#define            SPI_IER_8_3_MSK2_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_3_MSK1_POS                                                                                  1
#define            SPI_IER_8_3_MSK1_NUMB                                                                                 1
#define            SPI_IER_8_3_MSK1_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_3_MSK0_POS                                                                                  0
#define            SPI_IER_8_3_MSK0_NUMB                                                                                 1
#define            SPI_IER_8_3_MSK0_RES_VAL                                                                              0x0
//R/W

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            SPI_IER_16_0                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET*coeff16_arm+0)
#else
#define            SPI_IER_16_0                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_IER_OFFSET)
#endif


#define            SPI_IER_16_0_RESERVED_POS                                                                             5
#define            SPI_IER_16_0_RESERVED_NUMB                                                                            27
#define            SPI_IER_16_0_RESERVED_RES_VAL                                                                         0x0000000
//R

#define            SPI_IER_16_0_MSK4_POS                                                                                 4
#define            SPI_IER_16_0_MSK4_NUMB                                                                                1
#define            SPI_IER_16_0_MSK4_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_0_MSK3_POS                                                                                 3
#define            SPI_IER_16_0_MSK3_NUMB                                                                                1
#define            SPI_IER_16_0_MSK3_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_0_MSK2_POS                                                                                 2
#define            SPI_IER_16_0_MSK2_NUMB                                                                                1
#define            SPI_IER_16_0_MSK2_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_0_MSK1_POS                                                                                 1
#define            SPI_IER_16_0_MSK1_NUMB                                                                                1
#define            SPI_IER_16_0_MSK1_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_0_MSK0_POS                                                                                 0
#define            SPI_IER_16_0_MSK0_NUMB                                                                                1
#define            SPI_IER_16_0_MSK0_RES_VAL                                                                             0x0
//R/W



#ifndef DSP_ACCESS
#define            SPI_IER_16_2                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET*coeff16_arm+2)
#else
#define            SPI_IER_16_2                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_IER_OFFSET+1)
#endif


#define            SPI_IER_16_2_RESERVED_POS                                                                             5
#define            SPI_IER_16_2_RESERVED_NUMB                                                                            27
#define            SPI_IER_16_2_RESERVED_RES_VAL                                                                         0x0000000
//R

#define            SPI_IER_16_2_MSK4_POS                                                                                 4
#define            SPI_IER_16_2_MSK4_NUMB                                                                                1
#define            SPI_IER_16_2_MSK4_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_2_MSK3_POS                                                                                 3
#define            SPI_IER_16_2_MSK3_NUMB                                                                                1
#define            SPI_IER_16_2_MSK3_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_2_MSK2_POS                                                                                 2
#define            SPI_IER_16_2_MSK2_NUMB                                                                                1
#define            SPI_IER_16_2_MSK2_RES_VAL                                                                             0x0
//R/W

#define            SPI_IER_16_2_MSK1_POS                                                                                 1
#define            SPI_IER_16_2_MSK1_NUMB