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📄 spi.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#define            SPI_ISR_8_2_WAKEUP_POS                                                                                4
#define            SPI_ISR_8_2_WAKEUP_NUMB                                                                               1
#define            SPI_ISR_8_2_WAKEUP_RES_VAL                                                                            0x0
//R/W

#define            SPI_ISR_8_2_TX_UNDERFLOW_POS                                                                          3
#define            SPI_ISR_8_2_TX_UNDERFLOW_NUMB                                                                         1
#define            SPI_ISR_8_2_TX_UNDERFLOW_RES_VAL                                                                      0x0
//R/W

#define            SPI_ISR_8_2_RX_OVERFLOW_POS                                                                           2
#define            SPI_ISR_8_2_RX_OVERFLOW_NUMB                                                                          1
#define            SPI_ISR_8_2_RX_OVERFLOW_RES_VAL                                                                       0x0
//R/W

#define            SPI_ISR_8_2_WE_POS                                                                                    1
#define            SPI_ISR_8_2_WE_NUMB                                                                                   1
#define            SPI_ISR_8_2_WE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_2_RE_POS                                                                                    0
#define            SPI_ISR_8_2_RE_NUMB                                                                                   1
#define            SPI_ISR_8_2_RE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_3                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff8_arm+3)


#define            SPI_ISR_8_3_RESERVED_POS                                                                              5
#define            SPI_ISR_8_3_RESERVED_NUMB                                                                             27
#define            SPI_ISR_8_3_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_ISR_8_3_WAKEUP_POS                                                                                4
#define            SPI_ISR_8_3_WAKEUP_NUMB                                                                               1
#define            SPI_ISR_8_3_WAKEUP_RES_VAL                                                                            0x0
//R/W

#define            SPI_ISR_8_3_TX_UNDERFLOW_POS                                                                          3
#define            SPI_ISR_8_3_TX_UNDERFLOW_NUMB                                                                         1
#define            SPI_ISR_8_3_TX_UNDERFLOW_RES_VAL                                                                      0x0
//R/W

#define            SPI_ISR_8_3_RX_OVERFLOW_POS                                                                           2
#define            SPI_ISR_8_3_RX_OVERFLOW_NUMB                                                                          1
#define            SPI_ISR_8_3_RX_OVERFLOW_RES_VAL                                                                       0x0
//R/W

#define            SPI_ISR_8_3_WE_POS                                                                                    1
#define            SPI_ISR_8_3_WE_NUMB                                                                                   1
#define            SPI_ISR_8_3_WE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_3_RE_POS                                                                                    0
#define            SPI_ISR_8_3_RE_NUMB                                                                                   1
#define            SPI_ISR_8_3_RE_RES_VAL                                                                                0x0
//R/W

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            SPI_ISR_16_0                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff16_arm+0)
#else
#define            SPI_ISR_16_0                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_ISR_OFFSET)
#endif


#define            SPI_ISR_16_0_RESERVED_POS                                                                             5
#define            SPI_ISR_16_0_RESERVED_NUMB                                                                            27
#define            SPI_ISR_16_0_RESERVED_RES_VAL                                                                         0x0000000
//R

#define            SPI_ISR_16_0_WAKEUP_POS                                                                               4
#define            SPI_ISR_16_0_WAKEUP_NUMB                                                                              1
#define            SPI_ISR_16_0_WAKEUP_RES_VAL                                                                           0x0
//R/W

#define            SPI_ISR_16_0_TX_UNDERFLOW_POS                                                                         3
#define            SPI_ISR_16_0_TX_UNDERFLOW_NUMB                                                                        1
#define            SPI_ISR_16_0_TX_UNDERFLOW_RES_VAL                                                                     0x0
//R/W

#define            SPI_ISR_16_0_RX_OVERFLOW_POS                                                                          2
#define            SPI_ISR_16_0_RX_OVERFLOW_NUMB                                                                         1
#define            SPI_ISR_16_0_RX_OVERFLOW_RES_VAL                                                                      0x0
//R/W

#define            SPI_ISR_16_0_WE_POS                                                                                   1
#define            SPI_ISR_16_0_WE_NUMB                                                                                  1
#define            SPI_ISR_16_0_WE_RES_VAL                                                                               0x0
//R/W

#define            SPI_ISR_16_0_RE_POS                                                                                   0
#define            SPI_ISR_16_0_RE_NUMB                                                                                  1
#define            SPI_ISR_16_0_RE_RES_VAL                                                                               0x0
//R/W



#ifndef DSP_ACCESS
#define            SPI_ISR_16_2                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff16_arm+2)
#else
#define            SPI_ISR_16_2                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_ISR_OFFSET+1)
#endif


#define            SPI_ISR_16_2_RESERVED_POS                                                                             5
#define            SPI_ISR_16_2_RESERVED_NUMB                                                                            27
#define            SPI_ISR_16_2_RESERVED_RES_VAL                                                                         0x0000000
//R

#define            SPI_ISR_16_2_WAKEUP_POS                                                                               4
#define            SPI_ISR_16_2_WAKEUP_NUMB                                                                              1
#define            SPI_ISR_16_2_WAKEUP_RES_VAL                                                                           0x0
//R/W

#define            SPI_ISR_16_2_TX_UNDERFLOW_POS                                                                         3
#define            SPI_ISR_16_2_TX_UNDERFLOW_NUMB                                                                        1
#define            SPI_ISR_16_2_TX_UNDERFLOW_RES_VAL                                                                     0x0
//R/W

#define            SPI_ISR_16_2_RX_OVERFLOW_POS                                                                          2
#define            SPI_ISR_16_2_RX_OVERFLOW_NUMB                                                                         1
#define            SPI_ISR_16_2_RX_OVERFLOW_RES_VAL                                                                      0x0
//R/W

#define            SPI_ISR_16_2_WE_POS                                                                                   1
#define            SPI_ISR_16_2_WE_NUMB                                                                                  1
#define            SPI_ISR_16_2_WE_RES_VAL                                                                               0x0
//R/W

#define            SPI_ISR_16_2_RE_POS                                                                                   0
#define            SPI_ISR_16_2_RE_NUMB                                                                                  1
#define            SPI_ISR_16_2_RE_RES_VAL                                                                               0x0

#ifndef DSP_ACCESS

#define            SPI_ISR_32                                                                                          REG32(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff32_arm)


#define            SPI_ISR_32_RESERVED_POS                                                                               5
#define            SPI_ISR_32_RESERVED_NUMB                                                                              27
#define            SPI_ISR_32_RESERVED_RES_VAL                                                                           0x0000000
//R

#define            SPI_ISR_32_WAKEUP_POS                                                                                 4
#define            SPI_ISR_32_WAKEUP_NUMB                                                                                1
#define            SPI_ISR_32_WAKEUP_RES_VAL                                                                             0x0
//R/W

#define            SPI_ISR_32_TX_UNDERFLOW_POS                                                                           3
#define            SPI_ISR_32_TX_UNDERFLOW_NUMB                                                                          1
#define            SPI_ISR_32_TX_UNDERFLOW_RES_VAL                                                                       0x0
//R/W

#define            SPI_ISR_32_RX_OVERFLOW_POS                                                                            2
#define            SPI_ISR_32_RX_OVERFLOW_NUMB                                                                           1
#define            SPI_ISR_32_RX_OVERFLOW_RES_VAL                                                                        0x0
//R/W

#define            SPI_ISR_32_WE_POS                                                                                     1
#define            SPI_ISR_32_WE_NUMB                                                                                    1
#define            SPI_ISR_32_WE_RES_VAL                                                                                 0x0
//R/W

#define            SPI_ISR_32_RE_POS                                                                                     0
#define            SPI_ISR_32_RE_NUMB                                                                                    1
#define            SPI_ISR_32_RE_RES_VAL                                                                                 0x0
//R/W


//SPI_IER
//-------------------
#define            SPI_IER_8_0                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_IER_OFFSET*coeff8_arm+0)


#define            SPI_IER_8_0_RESERVED_POS                                                                              5
#define            SPI_IER_8_0_RESERVED_NUMB                                                                             27
#define            SPI_IER_8_0_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_IER_8_0_MSK4_POS                                                                                  4
#define            SPI_IER_8_0_MSK4_NUMB                                                                                 1
#define            SPI_IER_8_0_MSK4_RES_VAL                                                                              0x0
//R/W

#define            SPI_IER_8_0_MSK3_POS                                                                                  3
#define            SPI_IER_8_0_MSK3_NUMB                                                                                 1
#define            SPI_IER_8_0_MSK3_RES_VAL                                                                              0x0

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