spi.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            SPI_SCR_32_AUTOIDLE_POS                                                                             0
#define            SPI_SCR_32_AUTOIDLE_NUMB                                                                            1
#define            SPI_SCR_32_AUTOIDLE_RES_VAL                                                                         0x0
//R


//SPI_SSR
//-------------------
#define            SPI_SSR_8_0                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff8_arm+0)


#define            SPI_SSR_8_0_RESERVED_POS                                                                              1
#define            SPI_SSR_8_0_RESERVED_NUMB                                                                             31
#define            SPI_SSR_8_0_RESERVED_RES_VAL                                                                          0x00000000
//R

#define            SPI_SSR_8_0_RESETDONE_POS                                                                             0
#define            SPI_SSR_8_0_RESETDONE_NUMB                                                                            1
#define            SPI_SSR_8_0_RESETDONE_RES_VAL                                                                         0x0
//R

#define            SPI_SSR_8_1                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff8_arm+1)


#define            SPI_SSR_8_1_RESERVED_POS                                                                              1
#define            SPI_SSR_8_1_RESERVED_NUMB                                                                             31
#define            SPI_SSR_8_1_RESERVED_RES_VAL                                                                          0x00000000
//R

#define            SPI_SSR_8_1_RESETDONE_POS                                                                             0
#define            SPI_SSR_8_1_RESETDONE_NUMB                                                                            1
#define            SPI_SSR_8_1_RESETDONE_RES_VAL                                                                         0x0
//R

#define            SPI_SSR_8_2                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff8_arm+2)


#define            SPI_SSR_8_2_RESERVED_POS                                                                              1
#define            SPI_SSR_8_2_RESERVED_NUMB                                                                             31
#define            SPI_SSR_8_2_RESERVED_RES_VAL                                                                          0x00000000
//R

#define            SPI_SSR_8_2_RESETDONE_POS                                                                             0
#define            SPI_SSR_8_2_RESETDONE_NUMB                                                                            1
#define            SPI_SSR_8_2_RESETDONE_RES_VAL                                                                         0x0
//R

#define            SPI_SSR_8_3                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff8_arm+3)


#define            SPI_SSR_8_3_RESERVED_POS                                                                              1
#define            SPI_SSR_8_3_RESERVED_NUMB                                                                             31
#define            SPI_SSR_8_3_RESERVED_RES_VAL                                                                          0x00000000
//R

#define            SPI_SSR_8_3_RESETDONE_POS                                                                             0
#define            SPI_SSR_8_3_RESETDONE_NUMB                                                                            1
#define            SPI_SSR_8_3_RESETDONE_RES_VAL                                                                         0x0
//R

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            SPI_SSR_16_0                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff16_arm+0)
#else
#define            SPI_SSR_16_0                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_SSR_OFFSET)
#endif


#define            SPI_SSR_16_0_RESERVED_POS                                                                             1
#define            SPI_SSR_16_0_RESERVED_NUMB                                                                            31
#define            SPI_SSR_16_0_RESERVED_RES_VAL                                                                         0x00000000
//R

#define            SPI_SSR_16_0_RESETDONE_POS                                                                            0
#define            SPI_SSR_16_0_RESETDONE_NUMB                                                                           1
#define            SPI_SSR_16_0_RESETDONE_RES_VAL                                                                        0x0
//R



#ifndef DSP_ACCESS
#define            SPI_SSR_16_2                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff16_arm+2)
#else
#define            SPI_SSR_16_2                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_SSR_OFFSET+1)
#endif


#define            SPI_SSR_16_2_RESERVED_POS                                                                             1
#define            SPI_SSR_16_2_RESERVED_NUMB                                                                            31
#define            SPI_SSR_16_2_RESERVED_RES_VAL                                                                         0x00000000
//R

#define            SPI_SSR_16_2_RESETDONE_POS                                                                            0
#define            SPI_SSR_16_2_RESETDONE_NUMB                                                                           1
#define            SPI_SSR_16_2_RESETDONE_RES_VAL                                                                        0x0

#ifndef DSP_ACCESS

#define            SPI_SSR_32                                                                                          REG32(SPI_BASE_ADDR_ARM+SPI_SSR_OFFSET*coeff32_arm)


#define            SPI_SSR_32_RESERVED_POS                                                                               1
#define            SPI_SSR_32_RESERVED_NUMB                                                                              31
#define            SPI_SSR_32_RESERVED_RES_VAL                                                                           0x00000000
//R

#define            SPI_SSR_32_RESETDONE_POS                                                                              0
#define            SPI_SSR_32_RESETDONE_NUMB                                                                             1
#define            SPI_SSR_32_RESETDONE_RES_VAL                                                                          0x0
//R


//SPI_ISR
//-------------------
#define            SPI_ISR_8_0                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff8_arm+0)


#define            SPI_ISR_8_0_RESERVED_POS                                                                              5
#define            SPI_ISR_8_0_RESERVED_NUMB                                                                             27
#define            SPI_ISR_8_0_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_ISR_8_0_WAKEUP_POS                                                                                4
#define            SPI_ISR_8_0_WAKEUP_NUMB                                                                               1
#define            SPI_ISR_8_0_WAKEUP_RES_VAL                                                                            0x0
//R/W

#define            SPI_ISR_8_0_TX_UNDERFLOW_POS                                                                          3
#define            SPI_ISR_8_0_TX_UNDERFLOW_NUMB                                                                         1
#define            SPI_ISR_8_0_TX_UNDERFLOW_RES_VAL                                                                      0x0
//R/W

#define            SPI_ISR_8_0_RX_OVERFLOW_POS                                                                           2
#define            SPI_ISR_8_0_RX_OVERFLOW_NUMB                                                                          1
#define            SPI_ISR_8_0_RX_OVERFLOW_RES_VAL                                                                       0x0
//R/W

#define            SPI_ISR_8_0_WE_POS                                                                                    1
#define            SPI_ISR_8_0_WE_NUMB                                                                                   1
#define            SPI_ISR_8_0_WE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_0_RE_POS                                                                                    0
#define            SPI_ISR_8_0_RE_NUMB                                                                                   1
#define            SPI_ISR_8_0_RE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_1                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff8_arm+1)


#define            SPI_ISR_8_1_RESERVED_POS                                                                              5
#define            SPI_ISR_8_1_RESERVED_NUMB                                                                             27
#define            SPI_ISR_8_1_RESERVED_RES_VAL                                                                          0x0000000
//R

#define            SPI_ISR_8_1_WAKEUP_POS                                                                                4
#define            SPI_ISR_8_1_WAKEUP_NUMB                                                                               1
#define            SPI_ISR_8_1_WAKEUP_RES_VAL                                                                            0x0
//R/W

#define            SPI_ISR_8_1_TX_UNDERFLOW_POS                                                                          3
#define            SPI_ISR_8_1_TX_UNDERFLOW_NUMB                                                                         1
#define            SPI_ISR_8_1_TX_UNDERFLOW_RES_VAL                                                                      0x0
//R/W

#define            SPI_ISR_8_1_RX_OVERFLOW_POS                                                                           2
#define            SPI_ISR_8_1_RX_OVERFLOW_NUMB                                                                          1
#define            SPI_ISR_8_1_RX_OVERFLOW_RES_VAL                                                                       0x0
//R/W

#define            SPI_ISR_8_1_WE_POS                                                                                    1
#define            SPI_ISR_8_1_WE_NUMB                                                                                   1
#define            SPI_ISR_8_1_WE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_1_RE_POS                                                                                    0
#define            SPI_ISR_8_1_RE_NUMB                                                                                   1
#define            SPI_ISR_8_1_RE_RES_VAL                                                                                0x0
//R/W

#define            SPI_ISR_8_2                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_ISR_OFFSET*coeff8_arm+2)


#define            SPI_ISR_8_2_RESERVED_POS                                                                              5
#define            SPI_ISR_8_2_RESERVED_NUMB                                                                             27
#define            SPI_ISR_8_2_RESERVED_RES_VAL                                                                          0x0000000
//R