spi.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            SPI_SCR_8_0_AUTOIDLE_RES_VAL                                                                        0x0
//R

#define            SPI_SCR_8_1                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff8_arm+1)


#define            SPI_SCR_8_1_RESERVED_0_POS                                                                            5
#define            SPI_SCR_8_1_RESERVED_0_NUMB                                                                           27
#define            SPI_SCR_8_1_RESERVED_0_RES_VAL                                                                        0x0000000
//R

#define            SPI_SCR_8_1_IDLEMODE_POS                                                                              3
#define            SPI_SCR_8_1_IDLEMODE_NUMB                                                                             2
#define            SPI_SCR_8_1_IDLEMODE_RES_VAL                                                                          0x0
//R/W

#define            SPI_SCR_8_1_ENAWAKEUP_POS                                                                             2
#define            SPI_SCR_8_1_ENAWAKEUP_NUMB                                                                            1
#define            SPI_SCR_8_1_ENAWAKEUP_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_1_SOFTRESET_POS                                                                             1
#define            SPI_SCR_8_1_SOFTRESET_NUMB                                                                            1
#define            SPI_SCR_8_1_SOFTRESET_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_1_AUTOIDLE_POS                                                                            0
#define            SPI_SCR_8_1_AUTOIDLE_NUMB                                                                           1
#define            SPI_SCR_8_1_AUTOIDLE_RES_VAL                                                                        0x0
//R

#define            SPI_SCR_8_2                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff8_arm+2)


#define            SPI_SCR_8_2_RESERVED_0_POS                                                                            5
#define            SPI_SCR_8_2_RESERVED_0_NUMB                                                                           27
#define            SPI_SCR_8_2_RESERVED_0_RES_VAL                                                                        0x0000000
//R

#define            SPI_SCR_8_2_IDLEMODE_POS                                                                              3
#define            SPI_SCR_8_2_IDLEMODE_NUMB                                                                             2
#define            SPI_SCR_8_2_IDLEMODE_RES_VAL                                                                          0x0
//R/W

#define            SPI_SCR_8_2_ENAWAKEUP_POS                                                                             2
#define            SPI_SCR_8_2_ENAWAKEUP_NUMB                                                                            1
#define            SPI_SCR_8_2_ENAWAKEUP_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_2_SOFTRESET_POS                                                                             1
#define            SPI_SCR_8_2_SOFTRESET_NUMB                                                                            1
#define            SPI_SCR_8_2_SOFTRESET_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_2_AUTOIDLE_POS                                                                            0
#define            SPI_SCR_8_2_AUTOIDLE_NUMB                                                                           1
#define            SPI_SCR_8_2_AUTOIDLE_RES_VAL                                                                        0x0
//R

#define            SPI_SCR_8_3                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff8_arm+3)


#define            SPI_SCR_8_3_RESERVED_0_POS                                                                            5
#define            SPI_SCR_8_3_RESERVED_0_NUMB                                                                           27
#define            SPI_SCR_8_3_RESERVED_0_RES_VAL                                                                        0x0000000
//R

#define            SPI_SCR_8_3_IDLEMODE_POS                                                                              3
#define            SPI_SCR_8_3_IDLEMODE_NUMB                                                                             2
#define            SPI_SCR_8_3_IDLEMODE_RES_VAL                                                                          0x0
//R/W

#define            SPI_SCR_8_3_ENAWAKEUP_POS                                                                             2
#define            SPI_SCR_8_3_ENAWAKEUP_NUMB                                                                            1
#define            SPI_SCR_8_3_ENAWAKEUP_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_3_SOFTRESET_POS                                                                             1
#define            SPI_SCR_8_3_SOFTRESET_NUMB                                                                            1
#define            SPI_SCR_8_3_SOFTRESET_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_3_AUTOIDLE_POS                                                                            0
#define            SPI_SCR_8_3_AUTOIDLE_NUMB                                                                           1
#define            SPI_SCR_8_3_AUTOIDLE_RES_VAL                                                                        0x0
//R

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            SPI_SCR_16_0                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff16_arm+0)
#else
#define            SPI_SCR_16_0                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_SCR_OFFSET)
#endif


#define            SPI_SCR_16_0_RESERVED_0_POS                                                                           5
#define            SPI_SCR_16_0_RESERVED_0_NUMB                                                                          27
#define            SPI_SCR_16_0_RESERVED_0_RES_VAL                                                                       0x0000000
//R

#define            SPI_SCR_16_0_IDLEMODE_POS                                                                             3
#define            SPI_SCR_16_0_IDLEMODE_NUMB                                                                            2
#define            SPI_SCR_16_0_IDLEMODE_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_16_0_ENAWAKEUP_POS                                                                            2
#define            SPI_SCR_16_0_ENAWAKEUP_NUMB                                                                           1
#define            SPI_SCR_16_0_ENAWAKEUP_RES_VAL                                                                        0x0
//R/W

#define            SPI_SCR_16_0_SOFTRESET_POS                                                                            1
#define            SPI_SCR_16_0_SOFTRESET_NUMB                                                                           1
#define            SPI_SCR_16_0_SOFTRESET_RES_VAL                                                                        0x0
//R/W

#define            SPI_SCR_16_0_AUTOIDLE_POS                                                                           0
#define            SPI_SCR_16_0_AUTOIDLE_NUMB                                                                          1
#define            SPI_SCR_16_0_AUTOIDLE_RES_VAL                                                                       0x0
//R



#ifndef DSP_ACCESS
#define            SPI_SCR_16_2                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff16_arm+2)
#else
#define            SPI_SCR_16_2                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_SCR_OFFSET+1)
#endif


#define            SPI_SCR_16_2_RESERVED_0_POS                                                                           5
#define            SPI_SCR_16_2_RESERVED_0_NUMB                                                                          27
#define            SPI_SCR_16_2_RESERVED_0_RES_VAL                                                                       0x0000000
//R

#define            SPI_SCR_16_2_IDLEMODE_POS                                                                             3
#define            SPI_SCR_16_2_IDLEMODE_NUMB                                                                            2
#define            SPI_SCR_16_2_IDLEMODE_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_16_2_ENAWAKEUP_POS                                                                            2
#define            SPI_SCR_16_2_ENAWAKEUP_NUMB                                                                           1
#define            SPI_SCR_16_2_ENAWAKEUP_RES_VAL                                                                        0x0
//R/W

#define            SPI_SCR_16_2_SOFTRESET_POS                                                                            1
#define            SPI_SCR_16_2_SOFTRESET_NUMB                                                                           1
#define            SPI_SCR_16_2_SOFTRESET_RES_VAL                                                                        0x0
//R/W

#define            SPI_SCR_16_2_AUTOIDLE_POS                                                                           0
#define            SPI_SCR_16_2_AUTOIDLE_NUMB                                                                          1
#define            SPI_SCR_16_2_AUTOIDLE_RES_VAL                                                                       0x0

#ifndef DSP_ACCESS

#define            SPI_SCR_32                                                                                          REG32(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff32_arm)


#define            SPI_SCR_32_RESERVED_0_POS                                                                             7
#define            SPI_SCR_32_RESERVED_0_NUMB                                                                            25
#define            SPI_SCR_32_RESERVED_0_RES_VAL                                                                         0x0000000
//R

#define            SPI_SCR_32_EMUSOFT_POS                                                                             	6
#define            SPI_SCR_32_EMUSOFT_NUMB                                                                            	1
#define            SPI_SCR_32_EMUSOFT_RES_VAL 										0x0
//R

#define            SPI_SCR_32_EMUFREE_POS                                                                             5
#define            SPI_SCR_32_EMUFREE_NUMB                                                                            1
#define            SPI_SCR_32_EMUFREE_RES_VAL                                                                         0x1
//R

#define            SPI_SCR_32_IDLEMODE_POS                                                                               3
#define            SPI_SCR_32_IDLEMODE_NUMB                                                                              2
#define            SPI_SCR_32_IDLEMODE_RES_VAL                                                                           0x0
//R/W

#define            SPI_SCR_32_ENAWAKEUP_POS                                                                              2
#define            SPI_SCR_32_ENAWAKEUP_NUMB                                                                             1
#define            SPI_SCR_32_ENAWAKEUP_RES_VAL                                                                          0x0
//R/W

#define            SPI_SCR_32_SOFTRESET_POS                                                                              1
#define            SPI_SCR_32_SOFTRESET_NUMB                                                                             1
#define            SPI_SCR_32_SOFTRESET_RES_VAL                                                                          0x0
//R/W