spi.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*Header modified by DSP-CONVERT V1.01 Script on  Tue Aug 13 14:51:46 MEST 2002*/
//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :spi.h
//
//   Date of Module Modification:4/15/02
//   Date of Generation :4/15/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _SPI__H
#define _SPI__H

//BEGIN INC GENERATION
//--------------------------------------


#ifndef DSP_ADJUST              /* If DSP_ADJUST is not defined, we are using */
#define DSP_ADJUST              /* include file for ARM code, we do not need any */
#endif                          /* modufucations. If this file is used for DSP code, */

//Register Offset
//-------------------
#define coeff8_arm   1
#define coeff16_arm  1
#define coeff32_arm  1

//-------------------

#define            SPI_REV_OFFSET                                                                                      (0x00 DSP_ADJUST)
#define            SPI_SCR_OFFSET                                                                                      (0x10 DSP_ADJUST)
#define            SPI_SSR_OFFSET                                                                                      (0x14 DSP_ADJUST)
#define            SPI_ISR_OFFSET                                                                                      (0x18 DSP_ADJUST)
#define            SPI_IER_OFFSET                                                                                      (0x1C DSP_ADJUST)
#define            SPI_SET1_OFFSET                                                                                     (0x24 DSP_ADJUST)
#define            SPI_SET2_OFFSET                                                                                     (0x28 DSP_ADJUST)
#define            SPI_CTRL_OFFSET                                                                                     (0x2C DSP_ADJUST)
#define            SPI_DSR_OFFSET                                                                                      (0x30 DSP_ADJUST)
#define            SPI_TX_OFFSET                                                                                       (0x34 DSP_ADJUST)
#define            SPI_RX_OFFSET                                                                                       (0x38 DSP_ADJUST)
#define            SPI_TEST_OFFSET                                                                                     (0x3C DSP_ADJUST)


#ifndef DSP_ACCESS


//SPI_REV
//-------------------
#define            SPI_REV_8_0                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff8_arm+0)


#define            SPI_REV_8_0_RESERVED_POS                                                                              8
#define            SPI_REV_8_0_RESERVED_NUMB                                                                             24
#define            SPI_REV_8_0_RESERVED_RES_VAL                                                                          0x000000
//R

#define            SPI_REV_8_0_REV_POS                                                                                   0
#define            SPI_REV_8_0_REV_NUMB                                                                                  8
#define            SPI_REV_8_0_REV_RES_VAL                                                                               0x20
//R

#define            SPI_REV_8_1                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff8_arm+1)


#define            SPI_REV_8_1_RESERVED_POS                                                                              8
#define            SPI_REV_8_1_RESERVED_NUMB                                                                             24
#define            SPI_REV_8_1_RESERVED_RES_VAL                                                                          0x000000
//R

#define            SPI_REV_8_1_REV_POS                                                                                   0
#define            SPI_REV_8_1_REV_NUMB                                                                                  8
#define            SPI_REV_8_1_REV_RES_VAL                                                                               0x20
//R

#define            SPI_REV_8_2                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff8_arm+2)


#define            SPI_REV_8_2_RESERVED_POS                                                                              8
#define            SPI_REV_8_2_RESERVED_NUMB                                                                             24
#define            SPI_REV_8_2_RESERVED_RES_VAL                                                                          0x000000
//R

#define            SPI_REV_8_2_REV_POS                                                                                   0
#define            SPI_REV_8_2_REV_NUMB                                                                                  8
#define            SPI_REV_8_2_REV_RES_VAL                                                                               0x20
//R

#define            SPI_REV_8_3                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff8_arm+3)


#define            SPI_REV_8_3_RESERVED_POS                                                                              8
#define            SPI_REV_8_3_RESERVED_NUMB                                                                             24
#define            SPI_REV_8_3_RESERVED_RES_VAL                                                                          0x000000
//R

#define            SPI_REV_8_3_REV_POS                                                                                   0
#define            SPI_REV_8_3_REV_NUMB                                                                                  8
#define            SPI_REV_8_3_REV_RES_VAL                                                                               0x20
//R

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            SPI_REV_16_0                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff16_arm+0)
#else
#define            SPI_REV_16_0                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_REV_OFFSET)
#endif


#define            SPI_REV_16_0_RESERVED_POS                                                                             8
#define            SPI_REV_16_0_RESERVED_NUMB                                                                            24
#define            SPI_REV_16_0_RESERVED_RES_VAL                                                                         0x000000
//R

#define            SPI_REV_16_0_REV_POS                                                                                  0
#define            SPI_REV_16_0_REV_NUMB                                                                                 8
#define            SPI_REV_16_0_REV_RES_VAL                                                                              0x20
//R



#ifndef DSP_ACCESS
#define            SPI_REV_16_2                                                                                        REG16(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff16_arm+2)
#else
#define            SPI_REV_16_2                                                                                        REG16(SPI_BASE_ADDR_DSP+SPI_REV_OFFSET+1)
#endif


#define            SPI_REV_16_2_RESERVED_POS                                                                             8
#define            SPI_REV_16_2_RESERVED_NUMB                                                                            24
#define            SPI_REV_16_2_RESERVED_RES_VAL                                                                         0x000000
//R

#define            SPI_REV_16_2_REV_POS                                                                                  0
#define            SPI_REV_16_2_REV_NUMB                                                                                 8
#define            SPI_REV_16_2_REV_RES_VAL                                                                              0x20

#ifndef DSP_ACCESS

#define            SPI_REV_32                                                                                          REG32(SPI_BASE_ADDR_ARM+SPI_REV_OFFSET*coeff32_arm)


#define            SPI_REV_32_RESERVED_POS                                                                               8
#define            SPI_REV_32_RESERVED_NUMB                                                                              24
#define            SPI_REV_32_RESERVED_RES_VAL                                                                           0x000000
//R

#define            SPI_REV_32_REV_POS                                                                                    0
#define            SPI_REV_32_REV_NUMB                                                                                   8
#define            SPI_REV_32_REV_RES_VAL                                                                                0x20
//R


//SPI_SCR
//-------------------
#define            SPI_SCR_8_0                                                                                         REG8(SPI_BASE_ADDR_ARM+SPI_SCR_OFFSET*coeff8_arm+0)


#define            SPI_SCR_8_0_RESERVED_0_POS                                                                            5
#define            SPI_SCR_8_0_RESERVED_0_NUMB                                                                           27
#define            SPI_SCR_8_0_RESERVED_0_RES_VAL                                                                        0x0000000
//R

#define            SPI_SCR_8_0_IDLEMODE_POS                                                                              3
#define            SPI_SCR_8_0_IDLEMODE_NUMB                                                                             2
#define            SPI_SCR_8_0_IDLEMODE_RES_VAL                                                                          0x0
//R/W

#define            SPI_SCR_8_0_ENAWAKEUP_POS                                                                             2
#define            SPI_SCR_8_0_ENAWAKEUP_NUMB                                                                            1
#define            SPI_SCR_8_0_ENAWAKEUP_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_0_SOFTRESET_POS                                                                             1
#define            SPI_SCR_8_0_SOFTRESET_NUMB                                                                            1
#define            SPI_SCR_8_0_SOFTRESET_RES_VAL                                                                         0x0
//R/W

#define            SPI_SCR_8_0_AUTOIDLE_POS                                                                            0
#define            SPI_SCR_8_0_AUTOIDLE_NUMB                                                                           1