wcdma_cks.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//CKS_PL_SEL_REG
//-------------------------
#define            CKS_PL_SEL_REG                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_PL_SEL_REG_OFFSET) << 2))
#define            CKS_PL_SEL_REG_RES_VAL                0x00000000
//R/W
//-------------------------



//CKS_CALIB_CNTL_REG1
//-------------------------
#define            CKS_CALIB_CNTL_REG1                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_CALIB_CNTL_REG1_OFFSET) << 2))
#define            CKS_CALIB_CNTL_REG1_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CKS_CALIB_CNTL_REG2
//-------------------------
#define            CKS_CALIB_CNTL_REG2                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_CALIB_CNTL_REG2_OFFSET) << 2))
#define            CKS_CALIB_CNTL_REG2_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CKS_CALIB_CNTL_REG3
//-------------------------
#define            CKS_CALIB_CNTL_REG3                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_CALIB_CNTL_REG3_OFFSET) << 2))
#define            CKS_CALIB_CNTL_REG3_RES_VAL                0x00000000
//R/W
//-------------------------



//CKS_SLP_CLK_CALIB_CYCLES_REG
//-------------------------
#define            CKS_SLP_CLK_CALIB_CYCLES_REG                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_SLP_CLK_CALIB_CYCLES_REG_OFFSET) << 2))
#define            CKS_SLP_CLK_CALIB_CYCLES_REG_RES_VAL                0x00000000
//R/W
//-------------------------



//CKS_SLP_CLK_CALIB_COUNT_REG
//-------------------------
#define            CKS_SLP_CLK_CALIB_COUNT_REG                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_SLP_CLK_CALIB_COUNT_REG_OFFSET) << 2))
#define            CKS_SLP_CLK_CALIB_COUNT_REG_RES_VAL                0x00000000
//R/W
//-------------------------



//CKS_CALIB_CLK_POS_EDGE_COUNT_REG
//-------------------------
#define            CKS_CALIB_CLK_POS_EDGE_COUNT_REG                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_CALIB_CLK_POS_EDGE_COUNT_REG_OFFSET) << 2))
#define            CKS_CALIB_CLK_POS_EDGE_COUNT_REG_RES_VAL                0x00000000
//R/W
//-------------------------



//CKS_CALIB_CLK_NEG_EDGE_COUNT_REG
//-------------------------
#define            CKS_CALIB_CLK_NEG_EDGE_COUNT_REG                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_CALIB_CLK_NEG_EDGE_COUNT_REG_OFFSET) << 2))
#define            CKS_CALIB_CLK_NEG_EDGE_COUNT_REG_RES_VAL                0x00000000
//R/W
//-------------------------



//CKS_PMT_SEL_REG
//-------------------------
#define            CKS_PMT_SEL_REG                        REG32(WCDMA_CS_LB+((WCDMA_CKS_BASE_ADDR+CKS_PMT_SEL_REG_OFFSET) << 2))
#define            CKS_PMT_SEL_REG_RES_VAL                0x0
//R/W
//-------------------------







#define             CKS_CLK_EN_REG1_RD_MASK    0x000F0400

#define             CKS_CLK_EN_REG1_WR_MASK    0x000F0400


#define             CKS_CLK_EN_REG2_RD_MASK    0x00017F1F

#define             CKS_CLK_EN_REG2_WR_MASK    0x00017F1F


#define             CKS_CLK_EN_REG3_RD_MASK    0x0000001F

#define             CKS_CLK_EN_REG3_WR_MASK    0x0000001F


#define             CKS_CLK_EN_REG4_RD_MASK    0x00010D0F

#define             CKS_CLK_EN_REG4_WR_MASK    0x0001000C


#define             CKS_SLP_EN_REG1_RD_MASK    0x000F0400

#define             CKS_SLP_EN_REG1_WR_MASK    0x000F0400


#define             CKS_SLP_EN_REG2_RD_MASK    0x00017F1F

#define             CKS_SLP_EN_REG2_WR_MASK    0x00017F1F


#define             CKS_SLP_EN_REG3_RD_MASK    0x0000001F

#define             CKS_SLP_EN_REG3_WR_MASK    0x0000001F


#define             CKS_SLP_EN_REG4_RD_MASK    0x00010D0F

#define             CKS_SLP_EN_REG4_WR_MASK    0x0001000C


#define             CKS_RST_EN_REG1_RD_MASK    0x000F0400

#define             CKS_RST_EN_REG1_WR_MASK    0x000F0400


#define             CKS_RST_EN_REG2_RD_MASK    0x00017F1F

#define             CKS_RST_EN_REG2_WR_MASK    0x00017F1F


#define             CKS_RST_EN_REG3_RD_MASK    0x0000001F

#define             CKS_RST_EN_REG3_WR_MASK    0x0000001F


#define             CKS_RST_EN_REG4_RD_MASK    0x0000010F

#define             CKS_RST_EN_REG4_WR_MASK    0x0000000E


#define             CKS_CLK_SEL_REG1_RD_MASK    0x77777777

#define             CKS_CLK_SEL_REG1_WR_MASK    0x77777777


#define             CKS_CLK_SEL_REG2_RD_MASK    0x07777777

#define             CKS_CLK_SEL_REG2_WR_MASK    0x07777777


#define             CKS_CLK_SEL_REG3_RD_MASK    0x77777777

#define             CKS_CLK_SEL_REG3_WR_MASK    0x77777777


#define             CKS_CLK_SEL_REG4_RD_MASK    0x03000FFF

#define             CKS_CLK_SEL_REG4_WR_MASK    0x03000FFF


#define             CKS_CLK_SEL_REG5_RD_MASK    0xF00C0003

#define             CKS_CLK_SEL_REG5_WR_MASK    0xF00C0003


#define             CKS_CLK_SEL_REG6_RD_MASK    0x00007777

#define             CKS_CLK_SEL_REG6_WR_MASK    0x00007777


#define             CKS_MDM_PDIV_SEL_REG_RD_MASK    0x00000103

#define             CKS_MDM_PDIV_SEL_REG_WR_MASK    0x00000103


#define             CKS_CLKOFF_EN_REG_RD_MASK    0x00000001

#define             CKS_CLKOFF_EN_REG_WR_MASK    0x00000001


#define             CKS_PL_CNTL_REG_RD_MASK    0x00000001

#define             CKS_PL_CNTL_REG_WR_MASK    0x00000001


#define             CKS_PL_SEL_REG_RD_MASK    0x0000000F

#define             CKS_PL_SEL_REG_WR_MASK    0x0000000F


#define             CKS_CALIB_CNTL_REG1_RD_MASK    0x00000001
//The CKS_CALIB_CNTL_REG1 reg has no write-able bits


#define             CKS_CALIB_CNTL_REG2_RD_MASK    0x00000001
//The CKS_CALIB_CNTL_REG2 reg has no write-able bits


#define             CKS_CALIB_CNTL_REG3_RD_MASK    0x00000003

#define             CKS_CALIB_CNTL_REG3_WR_MASK    0x00000003


#define             CKS_SLP_CLK_CALIB_CYCLES_REG_RD_MASK    0xFFFFFFFF

#define             CKS_SLP_CLK_CALIB_CYCLES_REG_WR_MASK    0xFFFFFFFF


#define             CKS_SLP_CLK_CALIB_COUNT_REG_RD_MASK    0xFFFFFFFF

#define             CKS_SLP_CLK_CALIB_COUNT_REG_WR_MASK    0x00000000


#define             CKS_CALIB_CLK_POS_EDGE_COUNT_REG_RD_MASK    0xFFFFFFFF

#define             CKS_CALIB_CLK_POS_EDGE_COUNT_REG_WR_MASK    0x00000000


#define             CKS_CALIB_CLK_NEG_EDGE_COUNT_REG_RD_MASK    0xFFFFFFFF

#define             CKS_CALIB_CLK_NEG_EDGE_COUNT_REG_WR_MASK    0x00000000


#define             CKS_PMT_SEL_REG_RD_MASK    0x1f

#define             CKS_PMT_SEL_REG_WR_MASK    0x1f

// Function prototype
void WCDMA_CksTestResetValue(void);
void WCDMA_CksTestRegistersAccess(void);

// Setup CKS module (clocks and resets) for generic setup
void WCDMA_CksSetupAllModules(void);

// Setup CKS module (clocks and resets) for RX Chain test
void WCDMA_CksSetupRXChainTest(void);

// Setup CKS module (clocks and resets) for RCI test
void WCDMA_CksSetupRCITest(void);

#endif