wcdma_psc.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 283 行
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283 行
//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2001, (C) Copyright 2001 Texas Instruments. All rights reserved
//
//========================================================================
#include "wcdma_mapping.h"
#ifndef _wcdma_psc__H
#define _wcdma_psc__H
//Standard Register offset list
#define PSC_VERSION_OFFSET 0x0000
#define PSC_F2_START_OFFSET 0x0001
#define PSC_NUM_TS_D_OFFSET 0x0002
#define PSC_NUM_C_OFFSET 0x0003
#define PSC_THRESHOLD_OFFSET 0x0004
#define PSC_CLEAR_FLAG_OFFSET 0x0005
#define PSC_PP_FLAG_OFFSET 0x0006
#define PSC_FUNCTION_OFFSET 0x0007
#define PSC_STATUS_OFFSET 0xA
#define PSC_NUM_PEAKS_OFFSET 0xB
#define PSC_MAX_OFFSET 0xC
#define PSC_MAX_POS_OFFSET 0xD
#define PSC_INT_RESET_OFFSET 0xE
#define PSC_INT_FLAG_OFFSET 0xF
#define PSC_RAM_TEST_OFFSET 0x1D
#define PSC_TEST_CMD_OFFSET 0x1E
#define PSC_PMT_CTRL_OFFSET 0x1F
//PSC_VERSION
//-------------------------
#define PSC_VERSION REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_VERSION_OFFSET) << 2))
#define PSC_VERSION_RES_VAL 0x00000005
//R/W
//No write to this reg are allowed
//-------------------------
//PSC_F2_START
//-------------------------
#define PSC_F2_START REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_F2_START_OFFSET) << 2))
#define PSC_F2_START_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_NUM_TS_D
//-------------------------
#define PSC_NUM_TS_D REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_NUM_TS_D_OFFSET) << 2))
#define PSC_NUM_TS_D_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_NUM_C
//-------------------------
#define PSC_NUM_C REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_NUM_C_OFFSET) << 2))
#define PSC_NUM_C_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_THRESHOLD
//-------------------------
#define PSC_THRESHOLD REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_THRESHOLD_OFFSET) << 2))
#define PSC_THRESHOLD_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_CLEAR_FLAG
//-------------------------
#define PSC_CLEAR_FLAG REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_CLEAR_FLAG_OFFSET) << 2))
#define PSC_CLEAR_FLAG_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_PP_FLAG
//-------------------------
#define PSC_PP_FLAG REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_PP_FLAG_OFFSET) << 2))
#define PSC_PP_FLAG_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_FUNCTION
//-------------------------
#define PSC_FUNCTION REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_FUNCTION_OFFSET) << 2))
#define PSC_FUNCTION_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_STATUS
//-------------------------
#define PSC_STATUS REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_STATUS_OFFSET) << 2))
#define PSC_STATUS_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//PSC_NUM_PEAKS
//-------------------------
#define PSC_NUM_PEAKS REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_NUM_PEAKS_OFFSET) << 2))
#define PSC_NUM_PEAKS_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//PSC_MAX
//-------------------------
#define PSC_MAX REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_MAX_OFFSET) << 2))
#define PSC_MAX_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//PSC_MAX_POS
//-------------------------
#define PSC_MAX_POS REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_MAX_POS_OFFSET) << 2))
#define PSC_MAX_POS_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//PSC_INT_RESET
//-------------------------
#define PSC_INT_RESET REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_INT_RESET_OFFSET) << 2))
#define PSC_INT_RESET_RES_VAL 0x00000000
//R/W
//-------------------------
//PSC_INT_FLAG
//-------------------------
#define PSC_INT_FLAG REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_INT_FLAG_OFFSET) << 2))
#define PSC_INT_FLAG_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//PSC_RAM_TEST
//-------------------------
#define PSC_RAM_TEST REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_RAM_TEST_OFFSET) << 2))
#define PSC_RAM_TEST_RES_VAL 0x00000000
//R/W
//no reads to this reg are allowed
//-------------------------
//PSC_TEST_CMD
//-------------------------
#define PSC_TEST_CMD REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_TEST_CMD_OFFSET) << 2))
#define PSC_TEST_CMD_RES_VAL 0x00000000
//R/W
//no reads to this reg are allowed
//-------------------------
//PSC_PMT_CTRL
//-------------------------
#define PSC_PMT_CTRL REG32(WCDMA_CS_LB+((WCDMA_PSC_BASE_ADDR+PSC_PMT_CTRL_OFFSET) << 2))
#define PSC_PMT_CTRL_RES_VAL 0x00000000
//R/W
//-------------------------
#define PSC_VERSION_RD_MASK 0x0000FFFF
//The PSC_VERSION reg has no write-able bits
#define PSC_F2_START_RD_MASK 0x00000001
#define PSC_F2_START_WR_MASK 0x00000001
#define PSC_NUM_TS_D_RD_MASK 0x0000003F
#define PSC_NUM_TS_D_WR_MASK 0x0000003F
#define PSC_NUM_C_RD_MASK 0x00000007
#define PSC_NUM_C_WR_MASK 0x00000007
#define PSC_THRESHOLD_RD_MASK 0x0000FFFF
#define PSC_THRESHOLD_WR_MASK 0x0000FFFF
#define PSC_CLEAR_FLAG_RD_MASK 0x00000001
#define PSC_CLEAR_FLAG_WR_MASK 0x00000001
#define PSC_PP_FLAG_RD_MASK 0x00000001
#define PSC_PP_FLAG_WR_MASK 0x00000001
#define PSC_FUNCTION_RD_MASK 0x00000001
#define PSC_FUNCTION_WR_MASK 0x00000001
#define PSC_STATUS_RD_MASK 0x00000003
//The PSC_STATUS reg has no write-able bits
#define PSC_NUM_PEAKS_RD_MASK 0x00001FFF
//The PSC_NUM_PEAKS reg has no write-able bits
#define PSC_MAX_RD_MASK 0x0000FFFF
//The PSC_MAX reg has no write-able bits
#define PSC_MAX_POS_RD_MASK 0x00001FFF
//The PSC_MAX_POS reg has no write-able bits
#define PSC_INT_RESET_RD_MASK 0x00000001
#define PSC_INT_RESET_WR_MASK 0x00000001
#define PSC_INT_FLAG_RD_MASK 0x00000003
//The PSC_INT_FLAG reg has no write-able bits
//The PSC_RAM_TEST reg has no read_able bits
#define PSC_RAM_TEST_WR_MASK 0x00000001
//The PSC_TEST_CMD reg has no read_able bits
#define PSC_TEST_CMD_WR_MASK 0x0000000F
#define PSC_PMT_CTRL_RD_MASK 0x0000001F
#define PSC_PMT_CTRL_WR_MASK 0x0000001F
// Function prototype
void WCDMA_PscTestResetValue(void);
void WCDMA_PscTestRegistersAccess(void);
#endif
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