hdq_1wire.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 319 行
H
319 行
//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename : hdq_1wire.h
//
// Date of Module Modification:3/8/01
// Date of Generation :3/22/01
//
//
//========================================================================
#include "mapping.h"
#ifndef _HDQ_1WIRE__H
#define _HDQ_1WIRE__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define HDQ_1WIRE_REVISION_REG_OFFSET 0x00
#define HDQ_1WIRE_TX_DATA_OFFSET 0x04
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_OFFSET 0x08
#define HDQ_1WIRE_CNTL_STATUS_REG_OFFSET 0x0C
#define HDQ_1WIRE_INTERRUPT_STATUS_OFFSET 0x10
#define HDQ_1WIRE_SYSCONFIG_REG_OFFSET 0x14
#define HDQ_1WIRE_SYSSTATUS_REG_OFFSET 0x18
//HDQ_1WIRE_REVISION_REG
//-------------------
#define HDQ_1WIRE_REVISION_REG REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_REVISION_REG_OFFSET)
#define HDQ_1WIRE_REVISION_REG_RESERVED_POS 8
#define HDQ_1WIRE_REVISION_REG_RESERVED_NUMB 24
#define HDQ_1WIRE_REVISION_REG_RESERVED_RES_VAL 0x0000
//R
#define HDQ_1WIRE_REVISION_REG_REVISION_NUM_POS 0
#define HDQ_1WIRE_REVISION_REG_REVISION_NUM_NUMB 8
#define HDQ_1WIRE_REVISION_REG_REVISION_NUM_RES_VAL 0x01
//R
//HDQ_1WIRE_TX_DATA
//-------------------
#define HDQ_1WIRE_TX_DATA REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_TX_DATA_OFFSET)
#define HDQ_1WIRE_TX_DATA_RESERVED_POS 8
#define HDQ_1WIRE_TX_DATA_RESERVED_NUMB 24
#define HDQ_1WIRE_TX_DATA_RESERVED_RES_VAL 0x0000
//R
#define HDQ_1WIRE_TX_DATA_WRITE_DATA_POS 0
#define HDQ_1WIRE_TX_DATA_WRITE_DATA_NUMB 8
#define HDQ_1WIRE_TX_DATA_WRITE_DATA_RES_VAL 0x00
//R/W
//HDQ_1WIRE_RX_RECEIVE_BUFFER_REG
//-------------------
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_OFFSET)
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_RESERVED_POS 8
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_RESERVED_NUMB 24
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_RESERVED_RES_VAL 0x0
//R
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_RECEIVED_CHARACTER_POS 0
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_RECEIVED_CHARACTER_NUMB 8
#define HDQ_1WIRE_RX_RECEIVE_BUFFER_REG_RECEIVED_CHARACTER_RES_VAL 0x00
//R
//HDQ_1WIRE_CNTL_STATUS_REG
//-------------------
#define HDQ_1WIRE_CNTL_STATUS_REG REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_CNTL_STATUS_REG_OFFSET)
#define HDQ_1WIRE_CNTL_STATUS_REG_RESERVED_POS 8
#define HDQ_1WIRE_CNTL_STATUS_REG_RESERVED_NUMB 24
#define HDQ_1WIRE_CNTL_STATUS_REG_RESERVED_RES_VAL 0x0000
//R
#define HDQ_1WIRE_CNTL_STATUS_REG_SINGLE_BIT_POS 7
#define HDQ_1WIRE_CNTL_STATUS_REG_SINGLE_BIT_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_SINGLE_BIT_RES_VAL 0x0
//R
#define HDQ_1WIRE_CNTL_STATUS_REG_INTERRUPT_MASK_POS 6
#define HDQ_1WIRE_CNTL_STATUS_REG_INTERRUPT_MASK_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_INTERRUPT_MASK_RES_VAL 0x0
//R/W
#define HDQ_1WIRE_CNTL_STATUS_REG_POWER_MODE_POS 5
#define HDQ_1WIRE_CNTL_STATUS_REG_POWER_MODE_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_POWER_MODE_RES_VAL 0x0
//R
#define HDQ_1WIRE_CNTL_STATUS_REG_GO_BIT_POS 4
#define HDQ_1WIRE_CNTL_STATUS_REG_GO_BIT_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_GO_BIT_RES_VAL 0x0
//R/W
#define HDQ_1WIRE_CNTL_STATUS_REG_PRESENCE_DETECT_POS 3
#define HDQ_1WIRE_CNTL_STATUS_REG_PRESENCE_DETECT_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_PRESENCE_DETECT_RES_VAL 0x0
//R
#define HDQ_1WIRE_CNTL_STATUS_REG_INIT_PULSE_POS 2
#define HDQ_1WIRE_CNTL_STATUS_REG_INIT_PULSE_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_INIT_PULSE_RES_VAL 0x0
//R/W
#define HDQ_1WIRE_CNTL_STATUS_REG_READ_WRITE_BIT_POS 1
#define HDQ_1WIRE_CNTL_STATUS_REG_READ_WRITE_BIT_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_READ_WRITE_BIT_RES_VAL 0x0
//R/W
#define HDQ_1WIRE_CNTL_STATUS_REG_MODE_BIT_POS 0
#define HDQ_1WIRE_CNTL_STATUS_REG_MODE_BIT_NUMB 1
#define HDQ_1WIRE_CNTL_STATUS_REG_MODE_BIT_RES_VAL 0x0
//R/W
//HDQ_1WIRE_INTERRUPT_STATUS
//-------------------
#define HDQ_1WIRE_INTERRUPT_STATUS REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_INTERRUPT_STATUS_OFFSET)
#define HDQ_1WIRE_INTERRUPT_STATUS_RESERVED_POS 3
#define HDQ_1WIRE_INTERRUPT_STATUS_RESERVED_NUMB 29
#define HDQ_1WIRE_INTERRUPT_STATUS_RESERVED_RES_VAL 0x0000
//R
#define HDQ_1WIRE_INTERRUPT_STATUS_TX_COMPLETE_POS 2
#define HDQ_1WIRE_INTERRUPT_STATUS_TX_COMPLETE_NUMB 1
#define HDQ_1WIRE_INTERRUPT_STATUS_TX_COMPLETE_RES_VAL 0x0
#define HDQ_1WIRE_INTERRUPT_STATUS_READ_COMPLETE_POS 1
#define HDQ_1WIRE_INTERRUPT_STATUS_READ_COMPLETE_NUMB 1
#define HDQ_1WIRE_INTERRUPT_STATUS_READ_COMPLETE_RES_VAL 0x0
//R
#define HDQ_1WIRE_INTERRUPT_STATUS_PRESENCE_TIMEOUT_POS 0
#define HDQ_1WIRE_INTERRUPT_STATUS_PRESENCE_TIMEOUT_NUMB 1
#define HDQ_1WIRE_INTERRUPT_STATUS_PRESENCE_TIMEOUT_RES_VAL 0x0
//R
//HDQ_1WIRE_SYSCONFIG_REG
//-------------------
#define HDQ_1WIRE_SYSCONFIG_REG REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_SYSCONFIG_REG_OFFSET)
#define HDQ_1WIRE_SYSCONFIG_REG_RESERVED_POS 2
#define HDQ_1WIRE_SYSCONFIG_REG_RESERVED_NUMB 30
#define HDQ_1WIRE_SYSCONFIG_REG_RESERVED_RES_VAL 0x0000
//R
#define HDQ_1WIRE_SYSCONFIG_REG_SOFTRESET_POS 1
#define HDQ_1WIRE_SYSCONFIG_REG_SOFTRESET_NUMB 1
#define HDQ_1WIRE_SYSCONFIG_REG_SOFTRESET_RES_VAL 0
//R/W
#define HDQ_1WIRE_SYSCONFIG_REG_AUTOIDLE_POS 0
#define HDQ_1WIRE_SYSCONFIG_REG_AUTOIDLE_NUMB 1
#define HDQ_1WIRE_SYSCONFIG_REG_AUTOIDLE_RES_VAL 0
//R/W
//HDQ_1WIRE_SYSSTATUS_REG
//-------------------
#define HDQ_1WIRE_SYSSTATUS_REG REG32(HDQ_1WIRE_BASE_ADDR_ARM+HDQ_1WIRE_SYSSTATUS_REG_OFFSET)
#define HDQ_1WIRE_SYSSTATUS_REG_RESERVED_POS 1
#define HDQ_1WIRE_SYSSTATUS_REG_RESERVED_NUMB 31
#define HDQ_1WIRE_SYSSTATUS_REG_RESERVED_RES_VAL 0x0000
//R
//bit value
#define HDQ_1WIRE_HIGH 0x1
#define HDQ_1WIRE_LOW 0X0
#define HDQ_MODE 0X0
#define WIRE_MODE 0x1
#define INT_ENABLE 0x1
#define INT_DISABLE 0x0
#define CLK_ENABLE 0x1
#define CLK_DISABLE 0x0
#define GO_BIT 0x1
#define INIT_PULSE 0x1
#define READ_BIT 0x1
#define WRITE_BIT 0x0
#define SINGLEBIT_MODE 0x1
/*############################################################################
NAME : HDQ_1WIRE_SET_BIT
DESCRIPTION : Modifies a bit in a 32 bits register
PARAMETERS : BitNumber : BIT(0..31) (Bit to modify)
Value : 0 / 1
RETURN VALUE:
LIMITATIONS : None
############################################################################*/
#define HDQ_1WIRE_SET_BIT(Address, BitNumber, Value) \
REG32(Address)=((Value)==0x0) ? \
(REG32(Address)&(~(0x1<<(BitNumber)))) : \
(REG32(Address)|(0x1<<(BitNumber)))
/*############################################################################
NAME : HDQ_1WIRE_CTRL_BIT
DESCRIPTION : Reads bit
PARAMETERS : BIT(0..31) : Control regist bit
RETURN VALUE: HIGH / LOW
LIMITATIONS : None
############################################################################*/
#define HDQ_1WIRE_CTRL_BIT(BitNumber) \
((HDQ_1WIRE_CNTL_STATUS_REG & (0x1<<(BitNumber)))>>(BitNumber))
/*############################################################################
NAME : HDQ_1WIRE_CTRL_ALL_BIT
DESCRIPTION : Reads bit
PARAMETERS : None
RETURN VALUE: HDQ_1WIRE control register value
LIMITATIONS : None
############################################################################*/
#define HDQ_1WIRE_CTRL_ALL_BIT() \
HDQ_1WIRE_CNTL_STATUS_REG
/*############################################################################
NAME : HDQ_1WIRE_SET_CTRL_BIT
DESCRIPTION : Defines hdq_1wire control register bit
PARAMETERS : BIT(0..31) : Bit to modify
HIGH/LOW
RETURN VALUE: None
LIMITATIONS : None
############################################################################*/
#define HDQ_1WIRE_SET_CTRL_BIT(BitNumber, value) \
HDQ_1WIRE_SET_BIT(HDQ_1WIRE_BASE_ADDR_ARM + HDQ_1WIRE_CNTL_STATUS_REG_OFFSET,BitNumber,value)
/*###########################################################################
NAME : HDQ_1WIRE_INT_STATUS_ALL_BIT
DESCRIPTION : Reads bit
PARAMETERS : None
RETURN VALUE: HDQ_1WIRE control register value
LIMITATIONS : None
############################################################################*/
#define HDQ_1WIRE_INT_STATUS_ALL_BIT() \
HDQ_1WIRE_INTERRUPT_STATUS
/*############################################################################
NAME : HDQ_1WIRE_INT_STATUS_BIT
DESCRIPTION : Reads bit
PARAMETERS : BIT(0..31) : Status register bit
RETURN VALUE: HIGH / LOW
LIMITATIONS : None
############################################################################*/
#define HDQ_1WIRE_INT_STATUS_BIT(BitNumber) \
((HDQ_1WIRE_INTERRUPT_STATUS & (0x1<<(BitNumber)))>>(BitNumber))
/*############################################################################
NAME : HDQ_1WIRE_REG_FIELD_READ_CHECK
DESCRIPTION : Defines hdq_1wire register read and field check
PARAMETERS : BIT(0..31) : Bit to modify
HIGH/LOW
RETURN VALUE: None
LIMITATIONS : None
############################################################################*/
#define CHECK_REG_VALUE(RegName, RealVal, ExpVal) \
if (ExpVal != RealVal) { \
RES_Set(RegName ## _BAD_READ_VALUE); \
RES_Set(START_ARRAY_DATA_ACCESS ); \
RES_Set(ExpVal); \
RES_Set(RealVal); \
RES_Set(END_ARRAY_DATA ); \
GlobalStatus=TEST_BAD; \
} \
#define CHECK_REG(RealVal, ExpVal) \
if (ExpVal != RealVal) { \
RES_Set(START_ARRAY_DATA_ACCESS ); \
RES_Set(ExpVal); \
RES_Set(RealVal); \
RES_Set(END_ARRAY_DATA ); \
GlobalStatus=TEST_BAD; \
} \
#endif
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