clkm2.h

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 205 行

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :CLKM2.h
//
//   Date of Generation :Fri Aug  4 11:10:27 2000
//
//
//========================================================================
#ifndef _CLKM2__H
#define _CLKM2__H

//BEGIN INC GENERATION
//--------------------------------------

#define     CLKM2_BASE_ADDR                           0xE1008000                 

//DSP_CKCTL
//-------------------
#define     DSP_CKCTL_REG                             REG16(CLKM2_BASE_ADDR+0x0)  

#define     TIMXO_POS                                 8                          
#define     TIMXO_NUMB                                1                          
#define     TIMXO_RES_VAL                             0x1                        
//R/W

#define     GPIOXO_POS                                7                          
#define     GPIOXO_NUMB                               1                          
#define     GPIOXO_RES_VAL                            0x1                        
//R/W

#define     GPIODIV_POS                               5                          
#define     GPIODIV_NUMB                              2                          
#define     GPIODIV_RES_VAL                           0x0                        
//R/W

#define     UARTXO_POS                                4                          
#define     UARTXO_NUMB                               1                          
#define     UARTXO_RES_VAL                            0x1                        
//R/W

#define     UARTDIV_POS                               2                          
#define     UARTDIV_NUMB                              2                          
#define     UARTDIV_RES_VAL                           0x2                        
//R/W

#define     DSP_PERDIV_POS                            0                          
#define     DSP_PERDIV_NUMB                           2                          
#define     DSP_PERDIV_RES_VAL                        0x2                        
//R/W



//DSP_IDLECT1
//-------------------
#define     DSP_IDLECT1_REG                           REG16(CLKM2_BASE_ADDR+0x4)  

#define     IDLTIM_DSP_POS                            8                          
#define     IDLTIM_DSP_NUMB                           81                         
#define     IDLTIM_DSP_RES_VAL                        0x0                        
//R/W

#define     IDLGPIO_DSP_POS                           7                          
#define     IDLGPIO_DSP_NUMB                          1                          
#define     IDLGPIO_DSP_RES_VAL                       0x0                        
//R/W

#define     IDLUART_DSP_POS                           3                          
#define     IDLUART_DSP_NUMB                          1                          
#define     IDLUART_DSP_RES_VAL                       0x0                        
//R/W

#define     IDLPER_DSP_POS                            2                          
#define     IDLPER_DSP_NUMB                           1                          
#define     IDLPER_DSP_RES_VAL                        0x0                        
//R/W

#define     IDLXORP_DSP_POS                           1                          
#define     IDLXORP_DSP_NUMB                          1                          
#define     IDLXORP_DSP_RES_VAL                       0x0                        
//R/W

#define     IDLWDT_DSP_POS                            0                          
#define     IDLWDT_DSP_NUMB                           1                          
#define     IDLWDT_DSP_RES_VAL                        0x0                        
//R/W



//DSP_IDLECT2
//-------------------
#define     DSP_IDLECT2_REG                           REG16(CLKM2_BASE_ADDR+0x8)  

#define     DSP_EN_TIMCK_POS                              5                          
#define     DSP_EN_TIMCK_NUMB                             1                          
#define     DSP_EN_TIMCK_RES_VAL                          0x0                        
//R/W

#define     DSP_EN_GPIOCK_POS                             4                          
#define     DSP_EN_GPIOCK_NUMB                            1                          
#define     DSP_EN_GPIOCK_RES_VAL                         0x0                        
//R/W

#define     DSP_EN_UARTCK_POS                             3                          
#define     DSP_EN_UARTCK_NUMB                            1                          
#define     DSP_EN_UARTCK_RES_VAL                         0x0                        
//R/W

#define     DSP_EN_PERCK_POS                              2                          
#define     DSP_EN_PERCK_NUMB                             1                          
#define     DSP_EN_PERCK_RES_VAL                          0x0                        
//R/W

#define     DSP_EN_XORPCK_POS                             1                          
#define     DSP_EN_XORPCK_NUMB                            1                          
#define     DSP_EN_XORPCK_RES_VAL                         0x0                        
//R/W

#define     DSP_EN_WDTCK_POS                              0                          
#define     DSP_EN_WDTCK_NUMB                             1                          
#define     DSP_EN_WDTCK_RES_VAL                          0x0                        
//R/W



//DSP_RSTCT2
//-------------------
#define     DSP_RSTCT2_REG                            REG16(CLKM2_BASE_ADDR+0x14)  

#define     PER_EN_POS                                0                          
#define     PER_EN_NUMB                               1                          
#define     PER_EN_RES_VAL                            0x0                        
//R/W



//DSP_SYSST
//-------------------
#define     DSP_SYSST_REG                             REG16(CLKM2_BASE_ADDR+0x18)  

#define     CLOCK_SELECT_POS                          11                         
#define     CLOCK_SELECT_NUMB                         3                          
#define     CLOCK_SELECT_RES_VAL                      unknown                    
//R

#define     CONFIG_POS                                7                          
#define     CONFIG_NUMB                               4                          
#define     CONFIG_RES_VAL                            unknown                    
//R

#define     IDLE_DSP_POS                              6                          
#define     IDLE_DSP_NUMB                             1                          
#define     IDLE_DSP_RES_VAL                          0x0                        
//R/W

#define     DSP_EXT_RST_POS                               5                          
#define     DSP_EXT_RST_NUMB                              1                          
#define     DSP_EXT_RST_RES_VAL                           0x0                        
//R/W

#define     POR_POS                                   5                          
#define     POR_NUMB                                  1                          
#define     POR_RES_VAL                               0x0                        
//R/W

#define     EXT_RST_POS                               4                          
#define     EXT_RST_NUMB                              1                          
#define     EXT_RST_RES_VAL                           0x0                        
//R/W

#define     DSP_ARM_RST_POS                           3                          
#define     DSP_ARM_RST_NUMB                          1                          
#define     DSP_ARM_RST_RES_VAL                       0x0                        
//R/W

#define     ARM_WDRST_POS                             2                          
#define     ARM_WDRST_NUMB                            1                          
#define     ARM_WDRST_RES_VAL                         0x0                        
//R/W

#define     GLOB_SWRST_POS                            1                          
#define     GLOB_SWRST_NUMB                           1                          
#define     GLOB_SWRST_RES_VAL                        0x0                        
//R/W

#define     DSP_WDRST_POS                             0                          
#define     DSP_WDRST_NUMB                            1                          
#define     DSP_WDRST_RES_VAL                         0x0                        
//R/W



// END INC GENERATION
//-------------------------------------------------------------

#endif