gdma.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 1,111 行 · 第 1/3 页
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#define DMA_CONFIG16_16_1 0xB10
#define DMA_CONFIG16_16_2 0xB11
#define DMA_CONFIG16_16_3 0xB12
#define DMA_CONFIG16_16_4 0xB13
#define DMA_CONFIG16_16_5 0xB14
#define DMA_CONFIG16_16_10 0xB19
#define DMA_CONFIG16_16_11 0xB22
#define DMA_CONFIG16_32_1 0xB20
#define DMA_CONFIG16_32_2 0xB21
#define DMA_CONFIG32_8_1 0xC00
#define DMA_CONFIG32_8_2 0xC01
#define DMA_CONFIG32_16_1 0xC10
#define DMA_CONFIG32_16_2 0xC11
#define DMA_CONFIG32_32_1 0xC20
#define DMA_CONFIG32_32_2 0xC21
#define DMA_CONFIG32_32_3 0xC22
#define DMA_CONFIG32_32_4 0xC23
#define DMA_CONFIG32_32_5 0xC24
#define DMA_CONFIG32_32_6 0xC25
#define DMA_CONFIG32_32_7 0xC26
#define DMA_CONFIG32_32_8 0xC27
#define DMA_CONFIG32_32_10 0xC29
#define DMA_CONFIG_LCD_32_0 0xCD0
#define DMA_CONFIG_LCD_32_1 0xCD1
#define DMA_CONFIG_LCD_32_2 0xCD2
#define DMA_CONFIG_LCD_32_3 0xCD3
#define DMA_CONFIG_LCD_16_0 0xCD4
#define DMA_CONFIG_CAMIF_32_CIF 0xCA0
#define DMA_CONFIG_CAMIF_32_QCIF 0xCA1
#define DMA_CONFIG_CAMIF_32_VGA 0xCA2
#define DMA_CONFIG_CAMIF_32_QVGA 0xCA3
#define DMA_CONFIG_CAMIF_32_VGA_3 0xCA4
#define DMA_CONFIG_MCBSP_32_0 0xCB0
#define DMA_CONFIG_MS_TX_32_0 0xCC0
#define DMA_CONFIG_MS_RX_32_0 0xCC1
#define DMA_CONFIG_UWIRE_TX 0xCC2
#define DMA_CONFIG_UWIRE_RX 0xCC3
#define UART_DMA_GEN 0xCC4
#define UARTMOD_MEM_TO_DMA_TO_THISUART_CONFIG 0xCC6
#define UARTMOD_UART_TO_DMA_TO_THISUART_CONFIG 0xCC7
#define UARTMOD_THISUART_TO_DMA_TO_MEM_CONFIG 0xCC8
#define UARTMOD_THISUART_TO_DMA_TO_UART_CONFIG 0xCC9
#define UARTBT_MEM_TO_DMA_TO_THISUART_CONFIG 0xCCA
#define UARTBT_UART_TO_DMA_TO_THISUART_CONFIG 0xCCB
#define UARTBT_THISUART_TO_DMA_TO_MEM_CONFIG 0xCCC
#define UARTBT_THISUART_TO_DMA_TO_UART_CONFIG 0xCCD
#define UARTEVAL_THISUART_TO_DMA_TO_MEM_CONFIG 0xCCE
#define UARTEVAL_THISUART_TO_DMA_TO_UART_CONFIG 0xCCF
#define UARTEVAL_MEM_TO_DMA_TO_THISUART_CONFIG 0xCE0
#define UARTEVAL_UART_TO_DMA_TO_THISUART_CONFIG 0xCE1
#define UARTMOD_MEM_TO_DMA_TO_THISUART_FIFO_CONFIG 0xCE2
#define UARTMOD_THISUART_TO_DMA_TO_MEM_FIFO_CONFIG 0xCE3
#define UARTBT_MEM_TO_DMA_TO_THISUART_FIFO_CONFIG 0xCE4
#define UARTBT_THISUART_TO_DMA_TO_MEM_FIFO_CONFIG 0xCE5
#define UARTEVAL_MEM_TO_DMA_TO_THISUART_FIFO_CONFIG 0xCE6
#define UARTEVAL_THISUART_TO_DMA_TO_MEM_FIFO_CONFIG 0xCE7
#define USB_DMA_CH2_TX 0xCF0
#define USB_DMA_CH1_TX 0xCF1
#define USB_DMA_CH0_TX 0xCF2
#define USB_DMA_CH2_RX 0xCF3
#define USB_DMA_CH1_RX 0xCF4
#define USB_DMA_CH0_RX 0xCF5
//Pattern
//----------------------
#define DMA_PATTERN_0 0
#define DMA_PATTERN_1 1
#define DMA_PATTERN_2 2
#define DMA_PATTERN_3 3
#define DMA_PATTERN_4 4
#define DMA_PATTERN_5 5
#define DMA_PATTERN_6 6
#define DMA_PATTERN_7 7
#define DMA_PATTERN_LCD_0 0xCD0
#define DMA_PATTERN_CAMIF_0 0xCA0
#define DMA_PATTERN_MCBSP_0 0xCB0
#define DMA_PATTERN_MS_0 0xCC0
#define DMA_PATTERN_UWIRE 0xCC2
#define DMA_PATTERN_UART 0xCC3
#define DMA_PATTERN_USB 0xCC4
//SrcMemWidth and DestMemWidth
//----------------------------
#define DMA_MEMWIDTH_8 0
#define DMA_MEMWIDTH_16 1
#define DMA_MEMWIDTH_32 2
// ----------------------------------------------------------
// Channel DMA global register structure
// ----------------------------------------------------------
typedef struct
{
BIT Free:1;
BIT AutogatingOn:1;
} GLOBAL_REGISTER ;
// ----------------------------------------------------------
// Channel DMA descriptor structure
// ----------------------------------------------------------
typedef struct
{
BIT ChannelNumb:4;
//DMA_CSDP
//--------------------
BIT TypeSize:2;
BIT SrcPort:3;
BIT DestPort:3;
BIT SrcPack:1;
BIT DestPack:1;
BIT SrcBurst:2;
BIT DestBurst:2;
//DMA_CCR
//-----------------------
BIT SyncNumb:5;
BIT SyncPr:1;
BIT EventSync:1;//fs
BIT Priority:1;
BIT Enable:1;
BIT Autoinit:1;
BIT Repeat:1;
BIT Fifofush:1;
BIT SrcAddressMode:2;
BIT DestAddressMode:2;
//DMA_CICR
//----------------------
BIT TimeoutIntEnable:1;
BIT DropIntEnable:1;
BIT HalfFrameIntEnable:1;
BIT FrameIntEnable:1;
BIT LastFrameIntEnable:1;
BIT BlockIntEnable:1;
//DMA_CSCR
//----------------------
BIT TimeoutInt:1;
BIT DropInt:1;
BIT HalfFrameInt:1;
BIT FrameInt:1;
BIT LastFrameInt:1;
BIT BlockInt:1;
//DMA_CSSA L and U
//----------------------
UWORD32 SrcAdd;
//DMA_CDSA L and U
//----------------------
UWORD32 DestAdd;
//DMA_CEN
//----------------------
UWORD16 EltNumber;
//DMA_CFN
//----------------------
UWORD16 FrameNumber;
//DMA_CEI
//----------------------
UWORD16 EltIndex;
//DMA_CFI
//----------------------
UWORD16 FrameIndex;
//-------------------------------------------------------------------
//Patern use to prepare data to transfert (use for test only)
//------------------------------------------------------------
UWORD16 Pattern;
}
CHANNEL_DESCRIPTOR ;
//=================================================================
//=================================================================
//DMA_LCD_CTRL
//------------
//FrameMode
#define DMA_LCD_FRAMEMODE_ONEFRAME 0
#define DMA_LCD_FRAMEMODE_TWOFRAME 1
#define DMA_LCD_FRAMEMODE_POS 0
#define DMA_LCD_FRAMEMODE_NUMB 1
#define DMA_LCD_FRAMEMODE_RESET_VAL 0
//----------------------------------------
//FrameIe
//ENABLE or DISABLE
#define DMA_LCD_FRAMEIE_POS 1
#define DMA_LCD_FRAMEIE_NUMB 1
#define DMA_LCD_FRAMEIE_RESET_VAL 0
//----------------------------------------
//BusErrorIe
//ENABLE or DISABLE
#define DMA_LCD_BUSERROR_POS 2
#define DMA_LCD_BUSERROR_NUMB 1
#define DMA_LCD_BUSERROR_RESET_VAL 0
//----------------------------------------
//Frame1ItCond
//ENABLE or DISABLE
#define DMA_LCD_FRAME1IT_POS 3
#define DMA_LCD_FRAME1IT_NUMB 1
#define DMA_LCD_FRAME1IT_RESET_VAL 0
//----------------------------------------
//Frame2ItCond
//ENABLE or DISABLE
#define DMA_LCD_FRAME2IT_POS 4
#define DMA_LCD_FRAME2IT_NUMB 1
#define DMA_LCD_FRAME2IT_RESET_VAL 0
//----------------------------------------
//BusErrorItCond
//ENABLE or DISABLE
#define DMA_LCD_BUSERRORIT_POS 5
#define DMA_LCD_BUSERRORIT_NUMB 1
#define DMA_LCD_BUSERRORIT_RESET_VAL 0
//----------------------------------------
//Src
#define DMA_LCD_SDRAM_SRC 0
#define DMA_LCD_IMIF_SRC 1 // OCP_T1
#define DMA_LCD_OCP_T1 1
#define DMA_LCD_OCP_T2 2 // Local_Access_Port
#define DMA_LCD_SRC_POS 6
#define DMA_LCD_SRC_NUMB 1
#define DMA_LCD_SRC_RESET_VAL 0
//----------------------------------------
//DMA_LCD_TOP_F1_L
//---------------------------------------
#define DMA_LCD_TOP_F1_L_POS 0
#define DMA_LCD_TOP_F1_L_NUMB 16
#define DMA_LCD_TOP_F1_L_MASK 0x0000FFFF
//DMA_LCD_TOP_F1_U
//---------------------------------------
#define DMA_LCD_TOP_F1_U_POS 0
#define DMA_LCD_TOP_F1_U_NUMB 16
#define DMA_LCD_TOP_F1_U_MASK 0xFFFF0000
#define DMA_LCD_TOP_F1_RESET_VAL 0x0
//DMA_LCD_BOT_F1_L
//---------------------------------------
#define DMA_LCD_BOT_F1_L_POS 0
#define DMA_LCD_BOT_F1_L_NUMB 16
#define DMA_LCD_BOT_F1_L_MASK 0x0000FFFF
//DMA_LCD_BOT_F1_U
//---------------------------------------
#define DMA_LCD_BOT_F1_U_POS 0
#define DMA_LCD_BOT_F1_U_NUMB 16
#define DMA_LCD_BOT_F1_U_MASK 0xFFFF0000
#define DMA_LCD_BOT_F1_RESET_VAL 0x0
//DMA_LCD_TOP_F2_L
//---------------------------------------
#define DMA_LCD_TOP_F2_L_POS 0
#define DMA_LCD_TOP_F2_L_NUMB 16
#define DMA_LCD_TOP_F2_L_MASK 0x0000FFFF
//DMA_LCD_TOP_F2_U
//---------------------------------------
#define DMA_LCD_TOP_F2_U_POS 0
#define DMA_LCD_TOP_F2_U_NUMB 16
#define DMA_LCD_TOP_F2_U_MASK 0xFFFF0000
#define DMA_LCD_TOP_F2_RESET_VAL 0x0
//DMA_LCD_BOT_F2_L
//---------------------------------------
#define DMA_LCD_BOT_F2_L_POS 0
#define DMA_LCD_BOT_F2_L_NUMB 16
#define DMA_LCD_BOT_F2_L_MASK 0x0000FFFF
//DMA_LCD_BOT_F2_U
//---------------------------------------
#define DMA_LCD_BOT_F2_U_POS 0
#define DMA_LCD_BOT_F2_U_NUMB 16
#define DMA_LCD_BOT_F2_U_MASK 0xFFFF0000
#define DMA_LCD_BOT_F2_RESET_VAL 0x0
// ----------------------------------------------------------
// LCD Channel DMA descriptor structure
// ----------------------------------------------------------
typedef struct
{
//DMA_LCD_CTRL
//--------------------
BIT FrameMode:1;
BIT FrameItIe:1;
BIT BusErrorItIe:1;
BIT Frame1ItCond:1;
BIT Frame2ItCond:1;
BIT BusErrorItCond:1;
BIT LcdSrc:1;
//DMA_LCD_TOP_F1
//-----------------------
UWORD32 LcdTopF1;
//DMA_LCD_BOT_F1
//-----------------------
UWORD32 LcdBotF1;
//DMA_LCD_TOP_F2
//-----------------------
UWORD32 LcdTopF2;
//DMA_LCD_BOT_F2
//-----------------------
UWORD32 LcdBotF2;
}
LCD_CHANNEL_DESCRIPTOR ;
// ----------------------------------------------------------
// Complete DMA Structure
// ----------------------------------------------------------
typedef struct
{
//Global register
//--------------------
BIT Autogating_on:1;
BIT Free:1;
CHANNEL_DESCRIPTOR DmaChannel[DMA_NUMBER_OF_CHANNEL];
LCD_CHANNEL_DESCRIPTOR LcdChannel;
}
DMA_SYSTEM_STRUCT ;
// ----------------------------------------------------------
// Macro to access the DMA REGISTERS -
// ---------------------------------------------------------
#define DMA_ACC(global,ch_select,reg_select) REG16((DMA_ADDRESS | (global<<10) | (ch_select<<6) | (reg_select<<1)) )
// global values
#define NO_GLOB_REG 0
#define GLOB_REG 1
// initialize or verify mode
#define INITIALIZE_MEM 1
#define VERIFY_MEM 0
// reg_select when GLOBAL_REG
#define DMA_GCR 0
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