gdma.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 1,111 行 · 第 1/3 页
H
1,111 行
// ===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
//
// Modifications : 03/03/2000 : v-bour@ti.com, add prototype for :
// DMA_EnableIntFlags
// DMA_EnableLcdIntFlags
// ===============================================================================
#include "global_types.h"
#ifndef __GDMA__H__
#define __GDMA__H__
// DMA address
#define DMA_ADDRESS 0xFFFED800
// Total Number of channels
#define DMA_NUMBER_OF_CHANNEL 9
// ChannelNumb
#define DMA_CHANNEL_0 0
#define DMA_CHANNEL_1 1
#define DMA_CHANNEL_2 2
#define DMA_CHANNEL_3 3
#define DMA_CHANNEL_4 4
#define DMA_CHANNEL_5 5
#define DMA_CHANNEL_6 6
#define DMA_CHANNEL_7 7
#define DMA_CHANNEL_8 8
#define DMA_CHANNEL_LCD 12
//------------------------------------
// DMA global registers
//------------------------------------
//DMA_GCR
//--------
#define DMA_FREE_RUNNING 0x1
#define DMA_SUSPEND_RUNNING 0x0
#define DMA_FREE_POS 2
#define DMA_FREE_NUMB 1
#define DMA_FREE_RESET_VAL 0
//------------------------------------
#define DMA_AUTOGATE_ON 0x1
#define DMA_AUTOGATE_OFF 0x0
#define DMA_AUTOGATE_POS 3
#define DMA_AUTOGATE_NUMB 1
#define DMA_AUTOGATE_RESET_VAL 1
//------------------------------------
// Regular channel registers
//------------------------------------
//DMA_CSDP
//--------
// TypeSize
#define DMA_TYPE_8_BITS 0x0
#define DMA_TYPE_16_BITS 0x1
#define DMA_TYPE_32_BITS 0x2
#define DMA_TYPE_SIZE_POS 0
#define DMA_TYPE_SIZE_NUMB 2
#define DMA_TYPE_SIZE_RESET_VAL 0
//----------------------------------------
//SrcPort and DestPort
#define DMA_SDRAM 0x0
#define DMA_EMIF 0x1
#define DMA_IMIF 0x2
#define DMA_RHEA 0x3
#define DMA_LOCAL 0x4
#define DMA_RHEA_API 0x5
// OMAP source port
#define DMA_EMIFF 0x0
#define DMA_EMIFS 0x1
#define DMA_OCP_T1 0x2
#define DMA_TIPB 0x3
#define DMA_OCP_T2 0x4
#define DMA_MPUI 0x5
#define DMA_SRC_PORT_POS 2
#define DMA_SRC_PORT_NUMB 4
#define DMA_SRC_PORT_RESET_VAL 0
#define DMA_DEST_PORT_POS 9
#define DMA_DEST_PORT_NUMB 4
#define DMA_DEST_PORT_RESET_VAL 0
//----------------------------------------
//SrcPack and DestPack
#define DMA_PACKING 0x1
#define DMA_NO_PACKING 0x0
#define DMA_SRC_PACK_POS 6
#define DMA_SRC_PACK_NUMB 1
#define DMA_SRC_PACK_RESET_VAL 0
#define DMA_DEST_PACK_POS 13
#define DMA_DEST_PACK_NUMB 1
#define DMA_DEST_PACK_RESET_VAL 0
//----------------------------------------
//SrcBurst and DestBurst
#define DMA_SINGLE_BURST 0x0
#define DMA_BURST_4 0x2
#define DMA_BURST_8 0x3
#define DMA_SRC_BURST_POS 7
#define DMA_SRC_BURST_NUMB 2
#define DMA_SRC_BURST_RESET_VAL 0
#define DMA_DEST_BURST_POS 14
#define DMA_DEST_BURST_NUMB 2
#define DMA_DEST_BURST_RESET_VAL 0
//----------------------------------------
//DMA_CCR
//--------
//SyncNumb
#define DMA_NOT_SYNC 0x0
#define DMA_SYNC_1 0x1
#define DMA_SYNC_2 0x2
#define DMA_SYNC_3 0x3
#define DMA_SYNC_4 0x4
#define DMA_SYNC_5 0x5
#define DMA_SYNC_7 0x7
#define DMA_SYNC_CAMIF 0x14
#define DMA_SYNC_SPI_TX 0x10
#define DMA_SYNC_SPI_RX 0x11
#define DMA_SYNC_25 0x19
#define DMA_SYNCNUMB_POS 0
#define DMA_SYNCNUMB_NUMB 5 // H1-to-H2 porting mod (changed from 4)
#define DMA_SYNCNUMB_RESET_VAL 0
//----------------------------------------
// other values represent the Dma request number
//----------------------------------------
//SyncPr
#define DMA_WITH_RHEA 0x0
#define DMA_WITH_API 0x1
#define DMA_SYNCPR_POS 5
#define DMA_SYNCPR_NUMB 1
#define DMA_SYNCPR_RESET_VAL 0
//----------------------------------------
//fs
#define DMA_FRAME_SYNCHRONIZED 0x1
#define DMA_ELT_SYNCHRONIZED 0x0
#define DMA_FS_POS 5
#define DMA_FS_NUMB 1
#define DMA_FS_RESET_VAL 0
//----------------------------------------
//Priority
#define DMA_HIGH_PRIORITY 0x1
#define DMA_LOW_PRIORITY 0x0
#define DMA_PRIORITY_POS 6
#define DMA_PRIORITY_NUMB 1
#define DMA_PRIORITY_RESET_VAL 0
//----------------------------------------
//Enable transfert
#define DMA_ENABBLE_TRANSFERT 0x1
#define DMA_DISABLE_TRANSFERT 0x0
#define DMA_ENABBLE_POS 7
#define DMA_ENABLE_NUMB 1
#define DMA_ENABLE_RESET_VAL 0
//----------------------------------------
//Autoinit
#define DMA_AUTOINIT_ON 0x1
#define DMA_AUTOINIT_OFF 0x0
#define DMA_AUTOINIT_POS 8
#define DMA_AUTOINIT_NUMB 1
#define DMA_AUTOINIT_RESET_VAL 0
//----------------------------------------
//Repeat
#define DMA_REPEAT_ON 0x1
#define DMA_REPEAT_OFF 0x0
#define DMA_REPEAT_POS 9
#define DMA_REPEAT_NUMB 1
#define DMA_REPEAT_RESET_VAL 0
//----------------------------------------
//Fifoflush
#define DMA_FORCE_FLUSH 0x1
#define DMA_NO_FLUSH 0x0
#define DMA_FLUSH_POS 10
#define DMA_FLUSH_NUMB 1
#define DMA_FLUSH_RESET_VAL 0
//----------------------------------------
//SrcAddressing and DestAddressing
#define DMA_ADD_CONSTANT 0x0
#define DMA_ADD_POSTINC 0x1
#define DMA_ADD_SINGLE_INDEX 0x2
#define DMA_ADD_DOUBINDEX 0x3
#define DMA_SRC_AMODE_POS 12
#define DMA_SRC_AMODE_NUMB 2
#define DMA_SRC_AMODE_RESET_VAL 0
#define DMA_DEST_AMODE_POS 14
#define DMA_DEST_AMODE_NUMB 2
#define DMA_DEST_AMODE_RESET_VAL 0
//----------------------------------------
//DMA_CICR
//----------------------
// TimeoutIntEnable
// DropIntEnable
// HalfFrameIntEnable use ENABLE and DISABLE
// FrameIntEnable for all these bits
// LastFrameIntEnable
// BlockIntEnable
#define DMA_TOUTIE_POS 0
#define DMA_TOUTIE_NUMB 1
#define DMA_TOUTIE_RESET_VAL 1
#define DMA_DROPIE_POS 1
#define DMA_DROPIE_NUMB 1
#define DMA_DROPIE_RESET_VAL 1
#define DMA_HALFIE_POS 2
#define DMA_HALFIE_NUMB 1
#define DMA_HALFIE_RESET_VAL 0
#define DMA_FRAMEIE_POS 3
#define DMA_FRAMEIE_NUMB 1
#define DMA_FRAMEIE_RESET_VAL 0
#define DMA_LASTIE_POS 4
#define DMA_LASTIE_NUMB 1
#define DMA_LASTIE_RESET_VAL 0
#define DMA_BLOCKIE_POS 5
#define DMA_BLOCKIE_NUMB 1
#define DMA_BLOCKIE_RESET_VAL 0
//DMA_CSCR
//----------------------
// TimeoutInt
// DropInt
// HalfFrameInt
// FrameInt
// LastFrameInt
// BlockInt
#define DMA_INT_ABSENT 0
#define DMA_INT_PRESENT 1
#define DMA_TOUT_POS 0
#define DMA_TOUT_NUMB 1
#define DMA_TOUT_RESET_VAL 0
#define DMA_DROP_POS 1
#define DMA_DROP_NUMB 1
#define DMA_DROP_RESET_VAL 0
#define DMA_HALF_POS 2
#define DMA_HALF_NUMB 1
#define DMA_HALF_RESET_VAL 0
#define DMA_FRAME_POS 3
#define DMA_FRAME_NUMB 1
#define DMA_FRAME_RESET_VAL 0
#define DMA_LASTFRAME_POS 4
#define DMA_LASTFRAME_NUMB 1
#define DMA_LASTFRAME_RESET_VAL 0
#define DMA_BLOCK_POS 5
#define DMA_BLOCK_NUMB 1
#define DMA_BLOCK_RESET_VAL 0
#define DMA_SYNC_POS 6
#define DMA_SYNC_NUMB 1
#define DMA_SYNC_RESET_VAL 0
//DMA_CSSA_L
//----------------------
#define DMA_CSSA_L_POS 0
#define DMA_CSSA_L_NUMB 16
#define DMA_CSSA_L_MASK 0xFFFF
//DMA_CSSA_U
//----------------------
#define DMA_CSSA_U_POS 0
#define DMA_CSSA_U_NUMB 16
#define DMA_CSSA_U_MASK 0xFFFF0000
//DMA_CDSA_L
//----------------------
#define DMA_CDSA_L_POS 0
#define DMA_CDSA_L_NUMB 16
#define DMA_CDSA_L_MASK 0xFFFF
//DMA_CDSA_U
//----------------------
#define DMA_CDSA_U_POS 0
#define DMA_CDSA_U_NUMB 16
#define DMA_CDSA_U_MASK 0xFFFF0000
//DMA_CEN
//----------------------
#define DMA_CEN_POS 0
#define DMA_CEN_NUMB 16
#define DMA_CEN_MASK 0xFFFF
//DMA_CFN
//----------------------
#define DMA_CFN_POS 0
#define DMA_CFN_NUMB 16
#define DMA_CFN_MASK 0xFFFF
//DMA_CEI
//----------------------
#define DMA_CEI_POS 0
#define DMA_CEI_NUMB 16
#define DMA_CEI_MASK 0xFFFF
//DMA_CFI
//----------------------
#define DMA_CFI_POS 0
#define DMA_CFI_NUMB 16
#define DMA_CFI_MASK 0xFFFF
// DMA_CONFIG...
//------------------------
//new value for omnivision test
#define DMA_CONFIG_CAMIF_32_QCIF_TEST_LCD 0x1
#define DMA_CONFIG_CAMIF8_32_QCIF_TEST_LCD 0x2
#define DMA_CONFIG_CAMIF8_32_CIF_TEST_LCD 0x3
#define DMA_CONFIG_CAMIF24_32_QCIF_TEST_LCD 0x4
#define DMA_CONFIG_CAMIF64_32_QCIF_TEST_LCD 0x5
#define DMA_CONFIG8_8_1 0xA00
#define DMA_CONFIG8_8_2 0xA01
#define DMA_CONFIG8_8_3 0xA02
#define DMA_CONFIG8_8_4 0xA03
#define DMA_CONFIG8_8_5 0xA04
#define DMA_CONFIG8_8_6 0xA05
#define DMA_CONFIG8_8_10 0xA09
#define DMA_CONFIG8_16_1 0xA10
#define DMA_CONFIG8_16_2 0xA11
#define DMA_CONFIG8_32_1 0xA20
#define DMA_CONFIG8_32_2 0xA21
#define DMA_CONFIG16_8_1 0xB00
#define DMA_CONFIG16_8_2 0xB01
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?