neptune_fpga.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART2_SHDN_NUMB                                                     1
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART2_SHDN_RES_VAL                                                  0x1
//R/W

#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART1_SHDN_POS                                                      3
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART1_SHDN_NUMB                                                     1
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART1_SHDN_RES_VAL                                                  0x1
//R/W

#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_HS_ENVDD_AUDIO_POS                                                  2
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_HS_ENVDD_AUDIO_NUMB                                                 1
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_HS_ENVDD_AUDIO_RES_VAL                                              0x1
//R/W

#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_LCD_ENBKL_POS                                                       1
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_LCD_ENBKL_NUMB                                                      1
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_LCD_ENBKL_RES_VAL                                                   0x0
//R/W

#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_LCD_ENVDD_POS                                                       0
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_LCD_ENVDD_NUMB                                                      1
#define            FPGA_HANDSET_UART_SHUTDOWN_REG_FG_LCD_ENVDD_RES_VAL                                                   0x0
//R/W


//FPGA_IT_MASKING_REG
//-------------------
#define            FPGA_IT_MASKING_REG                                                                                 REG8(FPGA_BASE_ADDR_ARM+FPGA_IT_MASKING_REG_OFFSET)


#define            FPGA_IT_MASKING_REG_ETH_MASKIT_POS                                                                    1
#define            FPGA_IT_MASKING_REG_ETH_MASKIT_NUMB                                                                   1
#define            FPGA_IT_MASKING_REG_ETH_MASKIT_RES_VAL                                                                0x1
//R/W

#define            FPGA_IT_MASKING_REG_CODEC_MASKIT_POS                                                                  0
#define            FPGA_IT_MASKING_REG_CODEC_MASKIT_NUMB                                                                 1
#define            FPGA_IT_MASKING_REG_CODEC_MASKIT_RES_VAL                                                              0x1
//R/W


//FPGA_MISC_REG
//-------------------
#define            FPGA_MISC_REG                                                                                       REG8(FPGA_BASE_ADDR_ARM+FPGA_MISC_REG_OFFSET)


#define            FPGA_MISC_REG_FG_SERIAL_LCD_CS2_POS                                                                   5
#define            FPGA_MISC_REG_FG_SERIAL_LCD_CS2_NUMB                                                                  1
#define            FPGA_MISC_REG_FG_SERIAL_LCD_CS2_RES_VAL                                                               0x0
//R/W

#define            FPGA_MISC_REG_ELPDR_CLKREQ_POS                                                                        4
#define            FPGA_MISC_REG_ELPDR_CLKREQ_NUMB                                                                       1
#define            FPGA_MISC_REG_ELPDR_CLKREQ_RES_VAL                                                                    0x0
//R/W

#define            FPGA_MISC_REG_FG_JTAG_EN_POS                                                                          3
#define            FPGA_MISC_REG_FG_JTAG_EN_NUMB                                                                         1
#define            FPGA_MISC_REG_FG_JTAG_EN_RES_VAL                                                                      0x0
//R/W

#define            FPGA_MISC_REG_FG_ETM_BUF_EN_POS                                                                       2
#define            FPGA_MISC_REG_FG_ETM_BUF_EN_NUMB                                                                      1
#define            FPGA_MISC_REG_FG_ETM_BUF_EN_RES_VAL                                                                   0x1
//R/W

#define            FPGA_MISC_REG_FG_ISP2_ADR_POS                                                                         1
#define            FPGA_MISC_REG_FG_ISP2_ADR_NUMB                                                                        1
#define            FPGA_MISC_REG_FG_ISP2_ADR_RES_VAL                                                                     0x1
//R/W

#define            FPGA_MISC_REG_FG_ISP1_ADR_POS                                                                         0
#define            FPGA_MISC_REG_FG_ISP1_ADR_NUMB                                                                        1
#define            FPGA_MISC_REG_FG_ISP1_ADR_RES_VAL                                                                     0x0
//R/W


//FPGA_MISC2_REG
//-------------------
#define            FPGA_MISC2_REG                                                                                      REG8(FPGA_BASE_ADDR_ARM+FPGA_MISC2_REG_OFFSET)


#define            FPGA_MISC2_REG_FG_HS_IO1_POS                                                                          1
#define            FPGA_MISC2_REG_FG_HS_IO1_NUMB                                                                         1
#define            FPGA_MISC2_REG_FG_HS_IO1_RES_VAL                                                                      0x0
//R

#define            FPGA_MISC2_REG_FG_RF_BOARD_DET_POS                                                                    0
#define            FPGA_MISC2_REG_FG_RF_BOARD_DET_NUMB                                                                   1
#define            FPGA_MISC2_REG_FG_RF_BOARD_DET_RES_VAL                                                                0x0
//R


//FPGA_IT_REG
//-------------------
#define            FPGA_IT_REG                                                                                         REG8(FPGA_BASE_ADDR_ARM+FPGA_IT_REG_OFFSET)


#define            FPGA_IT_REG_CODEC_IRQ_POS                                                                             2
#define            FPGA_IT_REG_CODEC_IRQ_NUMB                                                                            1
#define            FPGA_IT_REG_CODEC_IRQ_RES_VAL                                                                         0x1
//R

#define            FPGA_IT_REG_ETH_IRQ_POS                                                                               1
#define            FPGA_IT_REG_ETH_IRQ_NUMB                                                                              1
#define            FPGA_IT_REG_ETH_IRQ_RES_VAL                                                                           0x1
//R


//FPGA_MUXDEMUX_MODE_REG
//-------------------
#define            FPGA_MUXDEMUX_MODE_REG                                                                              REG8(FPGA_BASE_ADDR_ARM+FPGA_MUXDEMUX_MODE_REG_OFFSET)


#define            FPGA_MUXDEMUX_MODE_REG_MUX_MODE_POS                                                                   0
#define            FPGA_MUXDEMUX_MODE_REG_MUX_MODE_NUMB                                                                  1
#define            FPGA_MUXDEMUX_MODE_REG_MUX_MODE_RES_VAL                                                               0x0
//R


//FPGA_SPI_REG
//-------------------
#define            FPGA_SPI_REG                                                                                        REG8(FPGA_BASE_ADDR_ARM+FPGA_SPI_REG_OFFSET)



//FPGA_UART1_REG
//-------------------
#define            FPGA_UART1_REG                                                                                      REG8(FPGA_BASE_ADDR_ARM+FPGA_UART1_REG_OFFSET)



//FPGA_UART2_REG
//-------------------
#define            FPGA_UART2_REG                                                                                      REG8(FPGA_BASE_ADDR_ARM+FPGA_UART2_REG_OFFSET)



//FPGA_UART3_REG
//-------------------
#define            FPGA_UART3_REG                                                                                      REG8(FPGA_BASE_ADDR_ARM+FPGA_UART3_REG_OFFSET)



//FPGA_MCBSP1_REG
//-------------------
#define            FPGA_MCBSP1_REG                                                                                     REG8(FPGA_BASE_ADDR_ARM+FPGA_MCBSP1_REG_OFFSET)



//FPGA_MCSI1_REG
//-------------------
#define            FPGA_MCSI1_REG                                                                                      REG8(FPGA_BASE_ADDR_ARM+FPGA_MCSI1_REG_OFFSET)



//FPGA_MCSI2_REG
//-------------------
#define            FPGA_MCSI2_REG                                                                                      REG8(FPGA_BASE_ADDR_ARM+FPGA_MCSI2_REG_OFFSET)



//FPGA_IRDA_REG
//-------------------
#define            FPGA_IRDA_REG                                                                                       REG8(FPGA_BASE_ADDR_ARM+FPGA_IRDA_REG_OFFSET)



//FPGA_TRITON_LOOPBACK_REG
//-------------------
#define            FPGA_TRITON_LOOPBACK_REG                                                                            REG8(FPGA_BASE_ADDR_ARM+FPGA_TRITON_LOOPBACK_REG_OFFSET)



//FPGA_TEST_REG
//-------------------
#define            FPGA_TEST_REG                                                                                       REG8(FPGA_BASE_ADDR_ARM+FPGA_TEST_REG_OFFSET)


#endif