📄 neptune_fpga.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :neptune_fpga.h
//
// Date of Module Modification:11/19/04
// Date of Generation :11/19/04
//
//
//========================================================================
#ifndef _FPGA__H
#define _FPGA__H
#include "mapping.h"
//Prototype
void FPGA_EnableUART1(void);
void FPGA_EnableUART2(void);
void FPGA_EnableUART3(void);
void FPGA_readtestreg(void);
UWORD8 FPGA_readversion(void);
UWORD8 FPGA_cpldreadversion(void);
void FPGA_Loop_Back_McBSP1_DX_2_DR(void);
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define FPGA_CPLD_REV_REG_OFFSET 0x0
#define FPGA_REV_REG_OFFSET 0x04
#define FPGA_QUICKSWITCH_CMD1_REG_OFFSET 0x10
#define FPGA_QUICKSWITCH_CMD2_REG2_OFFSET 0x12
#define FPGA_HANDSET_UART_SHUTDOWN_REG_OFFSET 0x14
#define FPGA_IT_MASKING_REG_OFFSET 0x16
#define FPGA_MISC_REG_OFFSET 0x18
#define FPGA_MISC2_REG_OFFSET 0x1A
#define FPGA_IT_REG_OFFSET 0x1C
#define FPGA_MUXDEMUX_MODE_REG_OFFSET 0x2
#define FPGA_SPI_REG_OFFSET 0x30
#define FPGA_UART1_REG_OFFSET 0x32
#define FPGA_UART2_REG_OFFSET 0x34
#define FPGA_UART3_REG_OFFSET 0x36
#define FPGA_MCBSP1_REG_OFFSET 0x38
#define FPGA_MCSI1_REG_OFFSET 0x3A
#define FPGA_MCSI2_REG_OFFSET 0x3C
#define FPGA_IRDA_REG_OFFSET 0x3E
#define FPGA_TRITON_LOOPBACK_REG_OFFSET 0x40
#define FPGA_TEST_REG_OFFSET 0x6
#define PALADIUM_CPLD_UART3_DOLO_OR_LOOPBACK_ADDR_OFFSET 0xF0
//FPGA_CPLD_REV_REG
//-------------------
#define FPGA_CPLD_REV_REG REG8(FPGA_BASE_ADDR_ARM+FPGA_CPLD_REV_REG_OFFSET)
#define PALADIUM_CPLD_UART3_DOLO_OR_LOOPBACK_ADDR REG8(FPGA_BASE_ADDR_ARM+PALADIUM_CPLD_UART3_DOLO_OR_LOOPBACK_ADDR_OFFSET)
#define FPGA_CPLD_REV_REG_MAJOR_REV_NUMBER_POS 4
#define FPGA_CPLD_REV_REG_MAJOR_REV_NUMBER_NUMB 4
#define FPGA_CPLD_REV_REG_MAJOR_REV_NUMBER_RES_VAL 0x0
//R
#define FPGA_CPLD_REV_REG_MINOR_REV_NUMBER_POS 0
#define FPGA_CPLD_REV_REG_MINOR_REV_NUMBER_NUMB 4
#define FPGA_CPLD_REV_REG_MINOR_REV_NUMBER_RES_VAL 0x0
//R
//FPGA_REV_REG
//-------------------
#define FPGA_REV_REG REG8(FPGA_BASE_ADDR_ARM+FPGA_REV_REG_OFFSET)
#define FPGA_REV_REG_MAJOR_REV_NUMBER_POS 4
#define FPGA_REV_REG_MAJOR_REV_NUMBER_NUMB 4
#define FPGA_REV_REG_MAJOR_REV_NUMBER_RES_VAL 0x0
//R
#define FPGA_REV_REG_MINOR_REV_NUMBER_POS 0
#define FPGA_REV_REG_MINOR_REV_NUMBER_NUMB 4
#define FPGA_REV_REG_MINOR_REV_NUMBER_RES_VAL 0x0
//R
//FPGA_QUICKSWITCH_CMD1_REG
//-------------------
#define FPGA_QUICKSWITCH_CMD1_REG REG8(FPGA_BASE_ADDR_ARM+FPGA_QUICKSWITCH_CMD1_REG_OFFSET)
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB2_POS 5
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB2_NUMB 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB2_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB1_ENB_POS 4
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB1_ENB_NUMB 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB1_ENB_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB1_POS 3
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB1_NUMB 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB1_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB12N_POS 2
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB12N_NUMB 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB12N_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB2_ENB_POS 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB2_ENB_NUMB 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB2_ENB_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB0_POS 0
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB0_NUMB 1
#define FPGA_QUICKSWITCH_CMD1_REG_FG_QS_USB0_RES_VAL 0x1
//R/W
//FPGA_QUICKSWITCH_CMD2_REG2
//-------------------
#define FPGA_QUICKSWITCH_CMD2_REG2 REG8(FPGA_BASE_ADDR_ARM+FPGA_QUICKSWITCH_CMD2_REG2_OFFSET)
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_I2S_ENB_POS 6
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_I2S_ENB_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_I2S_ENB_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_I2S_POS 5
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_I2S_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_I2S_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCBSP1_POS 4
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCBSP1_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCBSP1_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI2_ENB_POS 3
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI2_ENB_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI2_ENB_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI2_POS 2
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI2_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI2_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI1_ENB_POS 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI1_ENB_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI1_ENB_RES_VAL 0x1
//R/W
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI1_POS 0
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI1_NUMB 1
#define FPGA_QUICKSWITCH_CMD2_REG2_FG_QS_MCSI1_RES_VAL 0x1
//R/W
//FPGA_HANDSET_UART_SHUTDOWN_REG
//-------------------
#define FPGA_HANDSET_UART_SHUTDOWN_REG REG8(FPGA_BASE_ADDR_ARM+FPGA_HANDSET_UART_SHUTDOWN_REG_OFFSET)
#define FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART3_SHDN_POS 5
#define FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART3_SHDN_NUMB 1
#define FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART3_SHDN_RES_VAL 0x1
//R/W
#define FPGA_HANDSET_UART_SHUTDOWN_REG_FG_UART2_SHDN_POS 4
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