wcdma_ctr.h
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C头文件 代码 · 共 672 行 · 第 1/2 页
H
672 行
#define CTR_DECODER_dbg_RD_MASK 0x00000001
#define CTR_DECODER_dbg_WR_MASK 0x00000001
#define CTR_TFCI_cmd_0_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_0_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_1_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_1_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_2_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_2_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_3_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_3_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_4_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_4_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_5_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_5_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_6_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_6_WR_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_7_RD_MASK 0xFFFFFFFF
#define CTR_TFCI_cmd_7_WR_MASK 0xFFFFFFFF
//The CTR_CURRENT_cmd reg has no read_able bits
//The CTR_CURRENT_cmd reg has no write-able bits
#define CTR_CDBK_STATUS_RD_MASK 0xFFFFFFFF
//The CTR_CDBK_STATUS reg has no write-able bits
#define CTR_JOB_INFO_RD_MASK 0xFFFFFFFF
//The CTR_JOB_INFO reg has no write-able bits
#define CTR_CURRENT_state_RD_MASK 0xFFFFFFFF
//The CTR_CURRENT_state reg has no write-able bits
//RAM Locations
//CTR_PILOT_BASE_0
#define CTR_PILOT_BASE_0_OFFSET 0x9000
#define CTR_PILOT_BASE_0 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_0_OFFSET) << 2))
#define CTR_PILOT_BASE_0_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_0_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_1
#define CTR_PILOT_BASE_1_OFFSET 0x9001
#define CTR_PILOT_BASE_1 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_1_OFFSET) << 2))
#define CTR_PILOT_BASE_1_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_1_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_2
#define CTR_PILOT_BASE_2_OFFSET 0x9002
#define CTR_PILOT_BASE_2 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_2_OFFSET) << 2))
#define CTR_PILOT_BASE_2_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_2_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_3
#define CTR_PILOT_BASE_3_OFFSET 0x9003
#define CTR_PILOT_BASE_3 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_3_OFFSET) << 2))
#define CTR_PILOT_BASE_3_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_3_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_4
#define CTR_PILOT_BASE_4_OFFSET 0x9004
#define CTR_PILOT_BASE_4 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_4_OFFSET) << 2))
#define CTR_PILOT_BASE_4_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_4_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_5
#define CTR_PILOT_BASE_5_OFFSET 0x9005
#define CTR_PILOT_BASE_5 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_5_OFFSET) << 2))
#define CTR_PILOT_BASE_5_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_5_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_6
#define CTR_PILOT_BASE_6_OFFSET 0x9006
#define CTR_PILOT_BASE_6 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_6_OFFSET) << 2))
#define CTR_PILOT_BASE_6_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_6_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_7
#define CTR_PILOT_BASE_7_OFFSET 0x9007
#define CTR_PILOT_BASE_7 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_7_OFFSET) << 2))
#define CTR_PILOT_BASE_7_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_7_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_8
#define CTR_PILOT_BASE_8_OFFSET 0x9008
#define CTR_PILOT_BASE_8 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_8_OFFSET) << 2))
#define CTR_PILOT_BASE_8_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_8_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_9
#define CTR_PILOT_BASE_9_OFFSET 0x9009
#define CTR_PILOT_BASE_9 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_9_OFFSET) << 2))
#define CTR_PILOT_BASE_9_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_9_WR_MASK 0x0000FFFF
//-------------------------
//CTR_PILOT_BASE_2047
#define CTR_PILOT_BASE_2047_OFFSET 0x97ff
#define CTR_PILOT_BASE_2047 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_PILOT_BASE_2047_OFFSET) << 2))
#define CTR_PILOT_BASE_2047_RD_MASK 0x0000FFFF
#define CTR_PILOT_BASE_2047_WR_MASK 0x0000FFFF
//RAM Locations
//CTR_STATISTICS_BASE_0
#define CTR_STATISTICS_BASE_0_OFFSET 0x9800
#define CTR_STATISTICS_BASE_0 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_0_OFFSET) << 2))
#define CTR_STATISTICS_BASE_0_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_0_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_1
#define CTR_STATISTICS_BASE_1_OFFSET 0x9801
#define CTR_STATISTICS_BASE_1 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_1_OFFSET) << 2))
#define CTR_STATISTICS_BASE_1_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_1_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_2
#define CTR_STATISTICS_BASE_2_OFFSET 0x9802
#define CTR_STATISTICS_BASE_2 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_2_OFFSET) << 2))
#define CTR_STATISTICS_BASE_2_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_2_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_3
#define CTR_STATISTICS_BASE_3_OFFSET 0x9803
#define CTR_STATISTICS_BASE_3 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_3_OFFSET) << 2))
#define CTR_STATISTICS_BASE_3_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_3_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_4
#define CTR_STATISTICS_BASE_4_OFFSET 0x9804
#define CTR_STATISTICS_BASE_4 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_4_OFFSET) << 2))
#define CTR_STATISTICS_BASE_4_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_4_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_5
#define CTR_STATISTICS_BASE_5_OFFSET 0x9805
#define CTR_STATISTICS_BASE_5 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_5_OFFSET) << 2))
#define CTR_STATISTICS_BASE_5_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_5_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_6
#define CTR_STATISTICS_BASE_6_OFFSET 0x9806
#define CTR_STATISTICS_BASE_6 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_6_OFFSET) << 2))
#define CTR_STATISTICS_BASE_6_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_6_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_7
#define CTR_STATISTICS_BASE_7_OFFSET 0x9807
#define CTR_STATISTICS_BASE_7 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_7_OFFSET) << 2))
#define CTR_STATISTICS_BASE_7_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_7_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_8
#define CTR_STATISTICS_BASE_8_OFFSET 0x9808
#define CTR_STATISTICS_BASE_8 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_8_OFFSET) << 2))
#define CTR_STATISTICS_BASE_8_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_8_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_9
#define CTR_STATISTICS_BASE_9_OFFSET 0x9809
#define CTR_STATISTICS_BASE_9 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_9_OFFSET) << 2))
#define CTR_STATISTICS_BASE_9_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_9_WR_MASK 0x0000FFFF
//-------------------------
//CTR_STATISTICS_BASE_255
#define CTR_STATISTICS_BASE_255_OFFSET 0x98ff
#define CTR_STATISTICS_BASE_255 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_STATISTICS_BASE_255_OFFSET) << 2))
#define CTR_STATISTICS_BASE_255_RD_MASK 0x0000FFFF
#define CTR_STATISTICS_BASE_255_WR_MASK 0x0000FFFF
//RAM Locations
//CTR_TFCI_BASE_0
#define CTR_TFCI_BASE_0_OFFSET 0x8800
#define CTR_TFCI_BASE_0 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_0_OFFSET) << 2))
#define CTR_TFCI_BASE_0_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_0_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_1
#define CTR_TFCI_BASE_1_OFFSET 0x8801
#define CTR_TFCI_BASE_1 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_1_OFFSET) << 2))
#define CTR_TFCI_BASE_1_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_1_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_2
#define CTR_TFCI_BASE_2_OFFSET 0x8802
#define CTR_TFCI_BASE_2 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_2_OFFSET) << 2))
#define CTR_TFCI_BASE_2_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_2_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_3
#define CTR_TFCI_BASE_3_OFFSET 0x8803
#define CTR_TFCI_BASE_3 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_3_OFFSET) << 2))
#define CTR_TFCI_BASE_3_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_3_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_4
#define CTR_TFCI_BASE_4_OFFSET 0x8804
#define CTR_TFCI_BASE_4 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_4_OFFSET) << 2))
#define CTR_TFCI_BASE_4_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_4_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_5
#define CTR_TFCI_BASE_5_OFFSET 0x8805
#define CTR_TFCI_BASE_5 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_5_OFFSET) << 2))
#define CTR_TFCI_BASE_5_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_5_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_6
#define CTR_TFCI_BASE_6_OFFSET 0x8806
#define CTR_TFCI_BASE_6 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_6_OFFSET) << 2))
#define CTR_TFCI_BASE_6_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_6_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_7
#define CTR_TFCI_BASE_7_OFFSET 0x8807
#define CTR_TFCI_BASE_7 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_7_OFFSET) << 2))
#define CTR_TFCI_BASE_7_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_7_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_8
#define CTR_TFCI_BASE_8_OFFSET 0x8808
#define CTR_TFCI_BASE_8 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_8_OFFSET) << 2))
#define CTR_TFCI_BASE_8_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_8_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_9
#define CTR_TFCI_BASE_9_OFFSET 0x8809
#define CTR_TFCI_BASE_9 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_9_OFFSET) << 2))
#define CTR_TFCI_BASE_9_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_9_WR_MASK 0x0000001F
//-------------------------
//CTR_TFCI_BASE_1023
#define CTR_TFCI_BASE_1023_OFFSET 0x8bff
#define CTR_TFCI_BASE_1023 REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_BASE_1023_OFFSET) << 2))
#define CTR_TFCI_BASE_1023_RD_MASK 0x0000001F
#define CTR_TFCI_BASE_1023_WR_MASK 0x0000001F
//CTR_OUTBUF_ADDR
#define CTR_OUTBUF_ADDR_OFFSET 0x8300
#define CTR_OUTBUF_ADDR REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_OUTBUF_ADDR_OFFSET) << 2))
#define CTR_OUTBUF_ADDR_RD_MASK 0x00003FFF
#define CTR_OUTBUF_ADDR_WR_MASK 0x00003FFF
//CTR_OUTBUF_DATA
#define CTR_OUTBUF_DATA_OFFSET 0x8301
#define CTR_OUTBUF_DATA REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_OUTBUF_DATA_OFFSET) << 2))
#define CTR_OUTBUF_DATA_RD_MASK 0x0000001F
#define CTR_OUTBUF_DATA_WR_MASK 0x0000001F
//CTR_SYMB_ADDR
#define CTR_SYMB_ADDR_OFFSET 0x8310
#define CTR_SYMB_ADDR REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_SYMB_ADDR_OFFSET) << 2))
#define CTR_SYMB_ADDR_RD_MASK 0x00003FFF
#define CTR_SYMB_ADDR_WR_MASK 0x00003FFF
//CTR_SYMB_DATA
#define CTR_SYMB_DATA_OFFSET 0x8311
#define CTR_SYMB_DATA REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_SYMB_DATA_OFFSET) << 2))
#define CTR_SYMB_DATA_RD_MASK 0x0000001F
#define CTR_SYMB_DATA_WR_MASK 0x0000001F
// Function prototype
void WCDMA_CtrTestResetValue(void);
void WCDMA_CtrTestRegistersAccess(void);
#endif
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?