wcdma_ctr.h

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//========================================================================
//        TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2001,  (C) Copyright 2001 Texas Instruments. All rights reserved
//
//========================================================================


#include "wcdma_mapping.h"
#ifndef _wcdma_ctr__H
#define _wcdma_ctr__H

//Standard Register offset list


#define            CTR_EN_OFFSET                     0x00000000
#define            CTR_REVISION_OFFSET                     0x00000004
#define            CTR_INT_MASK_OFFSET                     0x00000010
#define            CTR_INT_STAT_OFFSET                     0x00008000
#define            CTR_SCAN_DISABLE_OFFSET                     0x00000020
#define            CTR_SCAN_BUSY_OFFSET                     0x00008010
#define            CTR_COMMAND_en_0_OFFSET                     0x00008020
#define            CTR_COMMAND_en_1_OFFSET                     0x00008021
#define            CTR_RECORD_en_0_OFFSET                     0x00008030
#define            CTR_RECORD_en_1_OFFSET                     0x00008031
#define            CTR_CLEAR_cmd_OFFSET                     0x00008040
#define            CTR_TFCI_DEBUG_OFFSET                     0x00000100
#define            CTR_DECODER_dbg_OFFSET                     0x00000101
#define            CTR_TFCI_cmd_0_OFFSET                     0x00008100
#define            CTR_TFCI_cmd_1_OFFSET                     0x00008101
#define            CTR_TFCI_cmd_2_OFFSET                     0x00008102
#define            CTR_TFCI_cmd_3_OFFSET                     0x00008103
#define            CTR_TFCI_cmd_4_OFFSET                     0x00008104
#define            CTR_TFCI_cmd_5_OFFSET                     0x00008105
#define            CTR_TFCI_cmd_6_OFFSET                     0x00008106
#define            CTR_TFCI_cmd_7_OFFSET                     0x00008107
#define            CTR_CURRENT_cmd_OFFSET                     0x00008110
#define            CTR_CDBK_STATUS_OFFSET                     0x00008111
#define            CTR_JOB_INFO_OFFSET                     0x00008112
#define            CTR_CURRENT_state_OFFSET                     0x00008113
//CTR_EN
//-------------------------
#define            CTR_EN                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_EN_OFFSET) << 2))
#define            CTR_EN_RES_VAL                0x00000000
//R/W
//no reads to this reg are allowed
//No write to this reg are allowed
//-------------------------



//CTR_REVISION
//-------------------------
#define            CTR_REVISION                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_REVISION_OFFSET) << 2))
#define            CTR_REVISION_RES_VAL                0x
//R/W
//no reads to this reg are allowed
//No write to this reg are allowed
//-------------------------



//CTR_INT_MASK
//-------------------------
#define            CTR_INT_MASK                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_INT_MASK_OFFSET) << 2))
#define            CTR_INT_MASK_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_INT_STAT
//-------------------------
#define            CTR_INT_STAT                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_INT_STAT_OFFSET) << 2))
#define            CTR_INT_STAT_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_SCAN_DISABLE
//-------------------------
#define            CTR_SCAN_DISABLE                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_SCAN_DISABLE_OFFSET) << 2))
#define            CTR_SCAN_DISABLE_RES_VAL                0x00000000
//R/W
//no reads to this reg are allowed
//No write to this reg are allowed
//-------------------------



//CTR_SCAN_BUSY
//-------------------------
#define            CTR_SCAN_BUSY                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_SCAN_BUSY_OFFSET) << 2))
#define            CTR_SCAN_BUSY_RES_VAL                0x00000000
//R/W
//no reads to this reg are allowed
//No write to this reg are allowed
//-------------------------



//CTR_COMMAND_en_0
//-------------------------
#define            CTR_COMMAND_en_0                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_COMMAND_en_0_OFFSET) << 2))
#define            CTR_COMMAND_en_0_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_COMMAND_en_1
//-------------------------
#define            CTR_COMMAND_en_1                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_COMMAND_en_1_OFFSET) << 2))
#define            CTR_COMMAND_en_1_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_RECORD_en_0
//-------------------------
#define            CTR_RECORD_en_0                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_RECORD_en_0_OFFSET) << 2))
#define            CTR_RECORD_en_0_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_RECORD_en_1
//-------------------------
#define            CTR_RECORD_en_1                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_RECORD_en_1_OFFSET) << 2))
#define            CTR_RECORD_en_1_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_CLEAR_cmd
//-------------------------
#define            CTR_CLEAR_cmd                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_CLEAR_cmd_OFFSET) << 2))
#define            CTR_CLEAR_cmd_RES_VAL                0x
//R/W
//no reads to this reg are allowed
//No write to this reg are allowed
//-------------------------



//CTR_TFCI_DEBUG
//-------------------------
#define            CTR_TFCI_DEBUG                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_DEBUG_OFFSET) << 2))
#define            CTR_TFCI_DEBUG_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_DECODER_dbg
//-------------------------
#define            CTR_DECODER_dbg                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_DECODER_dbg_OFFSET) << 2))
#define            CTR_DECODER_dbg_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_0
//-------------------------
#define            CTR_TFCI_cmd_0                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_0_OFFSET) << 2))
#define            CTR_TFCI_cmd_0_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_1
//-------------------------
#define            CTR_TFCI_cmd_1                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_1_OFFSET) << 2))
#define            CTR_TFCI_cmd_1_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_2
//-------------------------
#define            CTR_TFCI_cmd_2                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_2_OFFSET) << 2))
#define            CTR_TFCI_cmd_2_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_3
//-------------------------
#define            CTR_TFCI_cmd_3                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_3_OFFSET) << 2))
#define            CTR_TFCI_cmd_3_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_4
//-------------------------
#define            CTR_TFCI_cmd_4                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_4_OFFSET) << 2))
#define            CTR_TFCI_cmd_4_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_5
//-------------------------
#define            CTR_TFCI_cmd_5                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_5_OFFSET) << 2))
#define            CTR_TFCI_cmd_5_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_6
//-------------------------
#define            CTR_TFCI_cmd_6                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_6_OFFSET) << 2))
#define            CTR_TFCI_cmd_6_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_TFCI_cmd_7
//-------------------------
#define            CTR_TFCI_cmd_7                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_TFCI_cmd_7_OFFSET) << 2))
#define            CTR_TFCI_cmd_7_RES_VAL                0x00000000
//R/W
//-------------------------



//CTR_CURRENT_cmd
//-------------------------
#define            CTR_CURRENT_cmd                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_CURRENT_cmd_OFFSET) << 2))
#define            CTR_CURRENT_cmd_RES_VAL                0x00000000
//R/W
//no reads to this reg are allowed
//No write to this reg are allowed
//-------------------------



//CTR_CDBK_STATUS
//-------------------------
#define            CTR_CDBK_STATUS                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_CDBK_STATUS_OFFSET) << 2))
#define            CTR_CDBK_STATUS_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_JOB_INFO
//-------------------------
#define            CTR_JOB_INFO                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_JOB_INFO_OFFSET) << 2))
#define            CTR_JOB_INFO_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//CTR_CURRENT_state
//-------------------------
#define            CTR_CURRENT_state                        REG32(WCDMA_CS_LB+((WCDMA_CTR_BASE_ADDR+CTR_CURRENT_state_OFFSET) << 2))
#define            CTR_CURRENT_state_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------

#define             CTR_EN_RD_MASK    0x00000003

#define             CTR_EN_WR_MASK    0x00000003

//The CTR_EN reg has no read_able bits
//The CTR_EN reg has no write-able bits
//The CTR_REVISION reg has no read_able bits
//The CTR_REVISION reg has no write-able bits

#define             CTR_REVISION_RES_VAL    0x


#define             CTR_INT_MASK_RD_MASK    0x8000003F

#define             CTR_INT_MASK_WR_MASK    0x8000003F


#define             CTR_INT_STAT_RD_MASK    0xBFFFFFFF
//The CTR_INT_STAT reg has no write-able bits
//The CTR_SCAN_DISABLE reg has no read_able bits
//The CTR_SCAN_DISABLE reg has no write-able bits
//The CTR_SCAN_BUSY reg has no read_able bits
//The CTR_SCAN_BUSY reg has no write-able bits
#define             CTR_SCAN_DISABLE_RD_MASK    0x00000001
#define             CTR_SCAN_DISABLE_WR_MASK    0x00000001

#define             CTR_COMMAND_en_0_RD_MASK    0xFFFFFFFF
//The CTR_COMMAND_en_0 reg has no write-able bits


#define             CTR_COMMAND_en_1_RD_MASK    0xFFFFFFFF
//The CTR_COMMAND_en_1 reg has no write-able bits


#define             CTR_RECORD_en_0_RD_MASK    0xFFFFFFFF
//The CTR_RECORD_en_0 reg has no write-able bits


#define             CTR_RECORD_en_1_RD_MASK    0xFFFFFFFF
//The CTR_RECORD_en_1 reg has no write-able bits
//The CTR_CLEAR_cmd reg has no read_able bits
//The CTR_CLEAR_cmd reg has no write-able bits

#define             CTR_CLEAR_cmd_RES_VAL    0x


#define             CTR_TFCI_DEBUG_RD_MASK    0x00000007

#define             CTR_TFCI_DEBUG_WR_MASK    0x00000007