📄 neptune_frame_buffer.h
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#define FRAME_BUFFER_FBPU_CONTROL_8_3_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_8_3_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_3_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_3_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_8_3_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_3_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_3_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_8_3_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_3_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_3_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_8_3_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_3_MEM_PROT_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_0 REG16(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff16_arm+0)
#define FRAME_BUFFER_FBPU_CONTROL_16_0_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_16_0_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_0_CLK_FREE_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_0_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_16_0_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_0_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_0_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_16_0_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_0_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_0_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_16_0_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_0_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_0_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_16_0_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_0_MEM_PROT_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_2 REG16(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff16_arm+2)
#define FRAME_BUFFER_FBPU_CONTROL_16_2_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_16_2_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_2_CLK_FREE_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_2_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_16_2_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_2_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_2_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_16_2_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_2_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_2_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_16_2_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_2_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_16_2_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_16_2_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_16_2_MEM_PROT_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_32 REG32(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff32_arm)
#define FRAME_BUFFER_FBPU_CONTROL_32_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_32_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_32_CLK_FREE_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_32_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_32_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_32_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_32_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_32_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_32_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_32_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_32_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_32_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_32_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_32_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_32_MEM_PROT_RES_VAL 0x0
//R/W
//FRAME_BUFFER_FBPU_STATUS
//-------------------
#define FRAME_BUFFER_FBPU_STATUS_8_0 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff8_arm+0)
#define FRAME_BUFFER_FBPU_STATUS_8_0_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_8_0_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_0_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_8_0_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_8_0_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_0_IA_MEM_RES_VAL 0x0
//R/C
#define FRAME_BUFFER_FBPU_STATUS_8_1 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff8_arm+1)
#define FRAME_BUFFER_FBPU_STATUS_8_1_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_8_1_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_1_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_8_1_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_8_1_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_1_IA_MEM_RES_VAL 0x0
//R/C
#define FRAME_BUFFER_FBPU_STATUS_8_2 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff8_arm+2)
#define FRAME_BUFFER_FBPU_STATUS_8_2_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_8_2_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_2_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_8_2_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_8_2_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_2_IA_MEM_RES_VAL 0x0
//R/C
#define FRAME_BUFFER_FBPU_STATUS_8_3 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff8_arm+3)
#define FRAME_BUFFER_FBPU_STATUS_8_3_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_8_3_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_3_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_8_3_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_8_3_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_8_3_IA_MEM_RES_VAL 0x0
//R/C
#define FRAME_BUFFER_FBPU_STATUS_16_0 REG16(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff16_arm+0)
#define FRAME_BUFFER_FBPU_STATUS_16_0_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_16_0_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_16_0_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_16_0_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_16_0_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_16_0_IA_MEM_RES_VAL 0x0
//R/C
#define FRAME_BUFFER_FBPU_STATUS_16_2 REG16(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff16_arm+2)
#define FRAME_BUFFER_FBPU_STATUS_16_2_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_16_2_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_16_2_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_16_2_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_16_2_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_16_2_IA_MEM_RES_VAL 0x0
//R/C
#define FRAME_BUFFER_FBPU_STATUS_32 REG32(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_STATUS_OFFSET*coeff32_arm)
#define FRAME_BUFFER_FBPU_STATUS_32_RESET_POS 1
#define FRAME_BUFFER_FBPU_STATUS_32_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_32_RESET_RES_VAL 0x1
//R
#define FRAME_BUFFER_FBPU_STATUS_32_IA_MEM_POS 0
#define FRAME_BUFFER_FBPU_STATUS_32_IA_MEM_NUMB 1
#define FRAME_BUFFER_FBPU_STATUS_32_IA_MEM_RES_VAL 0x0
//R/C
#endif
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